1. Field of the Invention
The present invention relates to an active matrix substrate plate used in liquid crystal display apparatuses and a manufacturing method therefor, and relates in particular to an active matrix substrate plate having superior properties made by a manufacturing process based on simplified processing steps and improved yield.
2. Description of the Related Art
Active matrix type liquid crystal display apparatus using thin film transistors (abbreviated as TFT hereinbelow) as switching elements is constructed by placing a color filter substrate plate opposite to an active matrix substrate plate, in which independent pixel regions containing a TFT and a pixel electrode in each pixel region are arranged in a matrix, with an intervening liquid crystal layer. Also, a light blocking layer is provided on the color filter substrate plate or on the active matrix substrate plate in the TFT section and the boundary region in each pixel region.
An example of the circuit arrangement of the active matrix substrate plate is shown in FIG. 182. In FIG. 182, this active matrix substrate plate is formed such that a plurality of scanning lines 1011 are formed on a transparent insulation substrate plate and a plurality of parallel signal lines 1031 are formed on the transparent insulating substrate plate so as to cross the scanning lines at right angles across the gate insulation layer (not shown), and near the intersection of the scanning line and the signal line, an inverted staggered structure TFT 1060 comprised by a gate electrode 1012, an island-shaped semiconductor layer opposing the gate electrode across the gate insulation layer, and a pair of drain electrodes 1032 and source electrodes 1033 separated by a channel gap above the semiconductor layer. And in a window section Wd surrounded by a scanning line 1011 and a signal line 1031, there are provided a pixel electrode 1041 and an accumulation capacitance section 1070, in such a way that the gate electrode 1012 is connected to the scanning line 1011, the drain electrode 1032 to the signal line 1031, and the source electrode 1033 to the pixel electrode 1041.
The window section Wd and the scanning line 1011 and the signal line 1031 surrounding the window section, the region comprised by TFT 1060 are referred to as the xe2x80x9cpixel region Px,xe2x80x9d hereinbelow. A plurality of such pixel regions Px are arranged next to each other in a matrix pattern to construct a display surface Dp of the liquid crystal display apparatus.
The scanning lines 1011 are extended outside of the display surface Dp, and at the start end located at its tip, the scanning line terminal 1015 exposed on the surface of the active matrix substrate plate is formed. Also, each signal line 1031 is extended outside of the display surface Dp, and at the start end located at its tip, the signal line terminal 1035 exposed on the surface of the active matrix substrate plate is formed.
On the outside of the display surface Dp, a protective transistor 1080 may sometimes be attached for protecting the TFT connected to each signal line and scanning line, in case of excess current flow. And, the adjacent signal lines 1031, for the purpose of dispersing unexpected electrical shock and protecting the TFT in the pixel region, may sometimes be connected electrically to each other at the outside of the display surface Dp with a high resistance line.
On the outer peripheral section of the display surface Dp, for the purpose of preventing difficulties such as shorting between layers caused unexpected electrical shock generated on the active matrix substrate plate during the production by dispersing over all the wiring, or for the purpose of inspecting circuit defects, there are provided various kinds of peripheral circuits such as a gate-shut bus line 1091 for linking each scanning line 1011, a drain-shunt bus line 1092 for linking each signal line 1031, a connection section for connecting the gate-shunt bus line and the drain-shut bus line, inspection pads 1094 and 1095 for scanning lines and signal lines, respectively, and when manufacturing is completed, the peripheral circuits excepting the inspection pads are removed along with the substrate plate edge pieces.
The active matrix substrate plate having its edge pieces cutoff excepting the inspection pads is processed in such a way that respective scanning line terminals 1015 are connected to a not-shown scanning line driver, and the signal line terminals 1035 are connected to a not-shown signal line driver, and according to signals from respective drivers, specific individual pixel signals are input into the pixel electrode 1041 through each TFT 1060 in the pixel region.
The pixel electrode 1041 is disposed opposite to a common electrode 1014, and the liquid crystal in the pixel region is driven by applying a potential difference between the electrodes. There are two types of arrangement of the pixel electrode and the common electrode. In one type of configuration, as shown in FIG. 183A, the pixel electrode 1041 formed on the active matrix substrate plate and the common electrode 1014 formed over the entire display region of the color filter substrate plate are placed opposite to each other across the liquid crystal Lc, and this configuration is commonly called xe2x80x9ctwisted nematic type (referred to TN-type hereinbelow)xe2x80x9d. The other configuration is, as shown in FIG. 183B, pixel electrode 1041 formed in a comb-teeth shape and the common electrode 1014 formed in a comb-teeth shape on the active matrix substrate plate are placed opposite to each other non-contactingly. This configuration is commonly called xe2x80x9cin plane switching methodxe2x80x9d (referred to as the IPS type hereinbelow).
TFT 1060 has a gate electrode 1012 extending from the scanning line 1011 in each pixel region Px, an electrode (it is referred to as the drain electrode in the following) 1032 extending from the signal line 1031, an electrode (it is referred to as the source electrode, in the following) 1033 connected to the pixel electrode 1041, and when a scanning line signal is transmitted to the gate electrode 1012, drain electrode 1032 and source electrode 1033 selectively become conductive so that a pixel signal forwarded from the signal line 1031 is transmitted to the pixel electrode 1041, and the liquid crystal is driven by the potential difference generated between the pixel electrode 1041 and the common electrode 1014.
The accumulation capacitance section 1070 is comprised by an accumulation capacitance electrode 1071 and a common accumulation electrode 1072, and is provided for the purpose of holding the liquid crystal driving potential until the next selection signal is applied on the gate electrode 1012 by preventing, when the scanning line 1011 becomes non-selective, fluctuations in the potential caused by leaking of the liquid crystal driving potential applied on the pixel electrode 1041 through the TFT 1060 and the like. FIG. 182 shows a gate-storage type of capacitance accumulation in which the common accumulation electrode 1072 is connected to the forestage scanning line, but a common-storage type of capacitance accumulation in which the common accumulation electrode 1072 is connected to the common wiring 1013 may sometimes be used.
An example (for example, a Japanese Unpublished Patent Application, First Publication, Hei 9-120083) of manufacturing steps of active matrix substrate plate for a conventional TN-type liquid crystal display apparatus having the circuit configuration described above will be explained with reference to FIGS. 184A-184E. In this case, a combination of patterning and etching steps (referred to simply as etching hereinbelow) based on film deposition and photolithography technique is regarded as one processing step. Also, in the following explanations, the location where the pixel region 1041 of the active matrix substrate plate is formed will be referred to as the window Wd, the location where TFT 1060 is formed as the TFT section Tf, the location where the accumulation capacitance section 1071 is formed as the accumulation capacitance section Cp, and outer peripheral regions of the display surface Dp where peripheral circuits such as terminals are formed as the outer peripheral section Ss.
(Step 1) As shown in FIG. 184A, a metallic layer 1010 is formed on the glass plate 1001, and excepting the scanning line 1011 (not shown) and the gate electrode 1012 extending from the scanning line to the TFT section Tf, the scanning terminal 1015 extending to the outer periphery section Ss, and the common accumulation electrode 1072 of the accumulation capacitance section Cp, the metallic layer 1010 is removed by etching.
(Step 2) As shown in FIG. 184B, laminating successively the gate insulation layer 1002 and the semiconductor layer 1020, comprised by an amorphous silicon layer 1021 and an n+ amorphous silicon layer 1022, on the transparent insulation substrate plate, the semiconductor layer 1020 is removed excepting the TFT section Tf.
(Step 3) As shown in FIG. 184C, a metallic layer 1030 is formed on the transparent insulation substrate plate, and excepting the signal line 1031, signal line terminal 1035 extending from the signal line to the outer peripheral section Ss, drain electrode 1032, and source electrode 1033, the metallic layer 1030 is removed by etching. Next, using the remaining metallic layer as masking, the n+ amorphous silicon layer 1022 exposed at the channel gap 1023 in the TFT section is removed.
(Step 4) As shown in FIG. 184D, a protective insulation layer 1003 is formed on the transparent insulation substrate plate, and a first opening 1061 reaching the signal line terminal 1035 by punching through the protective insulation layer 1003 in the outer peripheral section Ss, a second opening 1062 reaching the source electrode 1033 by punching through the protective insulation layer 1003 in the TFT section Tf, and a third opening 1063 reaching the scanning line terminal 1015 by punching through the protective insulation layer 1003 and the gate insulation layer 1002 in the outer peripheral section Ss are formed by etching.
(Step 5) As shown in FIG. 184E, a transparent conductive layer 1040 is formed on the transparent insulation substrate plate, and excepting the pixel electrode 1041 extending to the window section Wd and connected to the source electrode 1033 through the second opening 1062 in the TFT section Tf, the accumulation capacitance electrode 1071 extending from the pixel electrode above the common accumulation electrode 1072 in the accumulation capacitance section Cp, the terminal pad 1095 exposed above the signal line terminal 1035 through the first opening 1061 and above the scanning line terminal 1015 through the third opening 1063 in the outer peripheral section Ss, the transparent conductive layer 1040 is removed by etching to complete the processing steps.
Although there have been many methods other than the process described above for manufacturing the active matrix substrate plates, when a combination of film depositing, patterning and etching processes is regarded as one processing step, all the conventional methods require five processing steps or more. However, in recent years, in place of cathode ray tubes as a display device for personal computers and monitors, liquid crystal display apparatuses are beginning to be used frequently, and along with this trend, there has been strong demand for lowering the cost of large liquid crystal display screens. Lowering the cost of liquid crystal display apparatus requires an integrated effort to lower the cost, but one element of such effort is simplification of the manufacturing process. Especially, if the photolithographic steps are increased, resulting higher number of processing steps leads to the necessity for large investments in facilities while increasing the probability of yield drop, methods of reducing the number of etching steps have been sought actively.
Further, according to the conventional manufacturing methods, to form peripheral circuits such as protective transistors, even more processing steps are sometimes required, and drop in yield caused by etching operation has also been experienced, which is caused by infiltration corrosion of needed underlying layers which should have been left intact.
Various methods for reducing the number of etching have been proposed in the past. For example, according to a Japanese Patent No. 2570255, Second Publication, and a Japanese Unpublished Patent Application, First Publication, Showa 63-15472, in step 1, scanning line and gate electrode are formed, in step 2, after forming films for gate insulation layer and semiconductor layer and metallic layer, excepting the regions where signal line and drain electrode and source electrode are continued, the metallic layer and the semiconductor layer are removed by etching, in step 3, after forming the transparent conductive layer, the transparent conductive layer and channel gap metallic layer are removed by etching except the signal line, the drain electrode, source electrode and pixel electrode extending from the source electrode, and next, removing the n+ amorphous silicon layer using the remaining transparent conductive layer as masking, and in step 4, after forming a protective insulation layer, the protective insulation layer on the pixel electrode is removed by etching, thus constituting a process comprised by four steps. However, according to this method, because the gate metallic layer and drain metallic layer are not electrically convertible, protective transistors cannot be formed, so that the yield has been a problem.
Also, a Japanese Unpublished Patent Application, First Publication, Hei 7-175084 discloses a process in which, in step 1, scanning line and gate electrode are formed, in step 2, after forming films of gate insulation layer and semiconductor layer, excepting the semiconductor layer of the TFT section, a gate insulation layer and semiconductor layer are removed by etching in step 3, after forming the transparent conductive layer, excepting the signal line, pixel electrode, drain electrode and source electrode, the transparent conductive layer is removed next, using the remaining transparent conductive layer as masking, n+ amorphous silicon layer is removed, and in step 4, after forming a protective insulation layer, the protective insulation layer above the pixel electrode is removed, thus constituting a process comprised by four steps. However, this method has a problem of quality of displays and the yield, because the signal lines, drain electrodes, source electrodes and others are made only of transparent conductive layer (ITO, indium tin oxide) that has high resistance and susceptible to causing film defects.
Further, a Japanese Unpublished Patent Application, First Publication, Hei 8-146462, proposes, in step 1, to form scanning line and gate electrode and in step 2, after forming films of the gate insulation layer, the semiconductor layer and metallic silicide layer, excepting the portions linking the signal line, drain electrode and source electrode, the metallic silicide layer, semiconductor layer, and gate insulation layer are removed by etching and in step 3, after forming films of the transparent conductive layer and metallic layer, excepting the signal line, drain electrode, source electrode and the pixel electrode linking the signal line, drain electrode and source electrode and pixel electrode linked to the source electrode, the metallic layer and the transparent conductive layer are removed by etching and next, using the remaining metallic layer as masking, removing the n+ amorphous silicon layer, and in step 4, after forming a protective insulation layer, the protective insulation layer above the pixel electrodes and the metallic layer are removed by etching, thereby constituting a 4-step process.
However, the methods according to a Japanese Unpublished Patent Application, First Publication, Hei 7-175084 and a Japanese Unpublished Patent Application, First Publication, Hei 8-146462, during etching of the metallic layer of signal lines and transparent conductive layer or protective insulation layer, due to infiltration of etching solution, signal line may be severed or the scanning lines in the lower layer and circuit elements of the gate electrodes and the like may become corroded and/or scanning line and signal line may become shorted, which cause poor yield or problems in the properties of the active matrix substrate plate, and therefore, it was difficult to put these techniques into practice.
The present invention is provided to resolve such forgoing problems, and therefore, the object is to provide an active matrix substrate plate that can be produced with good yield and superior properties using a lesser number of manufacturing steps and its manufacturing methods.
To resolve the subject matter, the active matrix substrate plate according to the first aspect of this invention is formed on a transparent insulating substrate plate having an array of pixel regions, wherein each pixel region contains a scanning line and a signal line and is surrounded by the scanning line and the signal line crossing each other at right angles, and in each pixel region is formed an inverted staggered structure thin film transistor comprised by a gate electrode, an island-shaped semiconductor layer opposing the gate electrode across a gate insulation layer, a pair of drain electrode and source electrode separated by a channel gap formed above the semiconductor layer, such that a pixel electrode is formed in a window section surrounded by the scanning line and the signal line for transmitting light, and the gate electrode is connected to the scanning line, the drain electrode is connected to the signal line, and the source electrode is connected to the pixel electrode (the TN-type active matrix substrate plate), wherein, the signal line, the source electrode and the drain electrode in all cases are formed by laminating a metallic layer on top of a transparent conductive layer, and the transparent conductive layer below the source electrode extends above the gate insulation layer of the window section so as to form the pixel electrode.
This TN-type active matrix substrate plate can be manufactured in four steps so that the productivity and the yield are improved.
Also, in this active matrix substrate plate, because the signal line is comprised by laminating a metallic layer and the transparent conductive layer, wiring resistance of the signal line can be reduced and the yield drop due to severing of lines can be suppressed, and because the source electrode and the pixel electrode are comprised integrally by the transparent conductive layer, an increase in the contact resistance can be suppressed and the performance properties are enhanced.
The active matrix substrate plate according to the second aspect of this invention is formed on a transparent insulating substrate plate by a plurality of scanning lines alternating with a plurality of common wiring lines, and a pixel region, containing a scanning line and a signal line is surrounded by the scanning line and the signal line crossing at right angles to each other, is arrayed in such a way that in each pixel region is formed an inverted staggered structure thin film transistor comprised by a gate electrode, an island-shaped semiconductor layer opposing the gate electrode across a gate insulation layer, a pair of drain electrode and source electrode separated by a channel gap formed above the semiconductor layer, such that in a window section surrounded by the scanning line and the signal line are formed a pixel electrode of a comb teeth shape and a common electrode of a comb teeth shape connecting to a common wiring line and opposing the pixel electrode, so that the gate electrode is connected to the scanning line, the drain electrode is connected to the signal line, and the source electrode is connected to the pixel electrode, so as to generate a horizontal electrical field with respect to the transparent insulating substrate plate between the pixel electrode and the common electrode(the IPS-type active matrix substrate plate), wherein, the common wiring line and the common electrode are both formed on a same layer as the scanning line, and at least in one perimeter section of the transparent insulating substrate plate, an end section of the common wiring line is formed so as to extend outside of an end section of the scanning line in the one perimeter section, and the end section of the common wiring line is linked to each other on the same layer as the scanning line.
This IPS-type active matrix substrate plate can be made in four steps so that the productivity and the yield are improved.
Also, in this active matrix substrate plate, the end section of the common wiring line extends outside of the end section of one perimeter section of the scanning line in the one perimeter section or opposing perimeter sections of the transparent insulating substrate plate, and the end section of the common wiring is linked to each other by the common wiring linking line, and the common wiring line terminal section is formed on the linking line, and therefore, regardless of whether the scanning line terminal is formed on one side or both sides of the transparent insulating substrate plate, the common wiring terminal can be led out, so that the IPS-type active matrix substrate plate can be produced independently.
Also, in this active matrix substrate plate, the difference in the height of the common electrode and pixel electrode section is made small, so that orientation control in the paneling step is facilitated.
The TN-type active matrix substrate plate according to the third aspect of this invention is comprised in such a way that a semiconductor layer of a same shape as the signal line is formed on a layer below the signal line and both the semiconductor layer and the signal line are covered by a transparent conductive layer, and the source electrode and the drain electrode are formed by laminating the transparent conductive layer on top of a metallic layer, and the transparent conductive layer in an upper layer of the source electrode extending above the gate insulation layer of the window section to form the pixel electrode.
This TN-type active matrix substrate plate can be manufactured in four steps so that the productivity and the yield are improved.
Also, in this active matrix substrate plate, because the signal line is comprised by a metallic layer and the transparent conductive layer, wiring resistance of the signal line can be reduced and the yield drop due to severing of lines can be suppressed, and because the source electrode and the pixel electrode are comprised integrally by the transparent conductive layer, an increase in the contact resistance can be suppressed and the performance properties are enhanced.
Also, in this active matrix substrate plate, the lateral surface of semiconductor layer below the signal line is covered by the transparent conductive layer, when etching the n+ amorphous silicon layer forming the TFT channel, infiltration corrosion of the amorphous layer of the semiconductor layer in the lateral direction can be prevented, thereby preventing difficulty of orientation control caused by improper covering by the protective insulation layer. Also, because the lateral surface of the metallic layer of the signal line is covered by the transparent conductive layer, when etching the transparent conductive layer, a photo-resist coating is covering the metallic layer of the signal line and the semiconductor layer. Therefore, even if debris or foreign particles are present on the metallic layer, etching solution does not infiltrate into the boundary of the transparent conductive layer and the metallic layer, to prevent severing of the signal line.
The TN-type active matrix substrate plate according to the fourth aspect of this invention is comprised in such a way that a semiconductor layer formed in a layer below the signal line is formed in a  cross sectional shape so as to have a wider bottom, and the upper layer of the -shaped semiconductor layer, a metallic layer and a transparent conductive layer comprising the signal line are formed so that the lateral surfaces are aligned, and the source electrode and the drain electrode are formed by laminating the transparent conductive layer on top of the metallic layer, and the pixel electrode is formed by the transparent conductive layer in an upper layer of the source electrode extending above the gate insulation layer of the window section.
This TN-type active matrix substrate plate can be manufactured in four steps so that the productivity and the yield are improved.
Also, in this active matrix substrate plate, because the signal line is comprised by a metallic layer and the transparent conductive layer, wiring resistance of the signal line can be reduced and the yield drop due to severing of lines can be suppressed, and because the source electrode and the pixel electrode are comprised integrally by the transparent conductive layer, an increase in the contact resistance can be suppressed and the properties are enhanced.
Also, in this active matrix substrate plate, at the time of forming the TFT channel, the metallic layer of the signal line can be etched using the transparent conductive layer as masking so that dimensional control of the signal line is facilitated.
The active matrix substrate plate according to the fifth aspect of this invention is a TN-type according to one of the second to the fourth aspects of this invention, wherein a thickness of an ohmic contact layer formed in an upper layer of the semiconductor layer formed in a layer below the source electrode and the drain electrode is 3-6 nm.
These TN-type active matrix substrate plates, in addition to the benefits recited above, when etching the drain and source electrodes, the ohmic contact layer above the semiconductor layer can be etched at the same time, and the thickness of the semiconductor layer can be made thin, so that the productivity is increased and the resistance in the vertical direction of the semiconductor layer can be lowered to improve the writing capability of the TFT.
The active matrix substrate plate according to the sixth aspect of this invention relates to one of the first to the fourth aspects of this invention, wherein the scanning line is comprised by a single film layer of Al or an alloy of primarily Al, or a lamination of a high melting point metal and an upper layer of Al or an alloy of primarily Al.
These active matrix substrate plates enable to reduce wiring resistance of the scanning line and to secure reliability of connection of the scanning line driver at the scanning line terminal section.
The active matrix substrate plate according to the seventh aspect of this invention relates to one of the first to the fourth aspects of this invention, wherein the scanning line is comprised by a lamination of conductive films of not less than two layers, and an uppermost layer of the lamination is comprised by a nitride film of a metal or a transparent conductive film.
These active matrix substrate plates enable to secure reliability of connection of the scanning line driver at the scanning line terminal section.
The active matrix substrate plates according to the eighth and the ninth aspects of this invention relate to the second and the fifth aspects of this invention, respectively, wherein the signal line is comprised by a lamination of a high melting point metal and an upper layer of Al or an alloy of primarily Al.
These active matrix substrate plates enable to reduce wiring resistance of the signal line and to secure reliability of connection of the signal line driver at the signal line terminal section.
The active matrix substrate plates according to the 10th and the 11th aspects of this invention relate to the second and the fifth aspects of this invention, respectively, wherein the scanning line is comprised by a lamination of conductive films of not less than two layers, and an uppermost layer of the lamination is comprised by a nitride film of a metal or a transparent conductive film.
These active matrix substrate plates enable to secure reliability of connection of the signal line driver at the signal line terminal section.
The active matrix substrate plates according to the 12th to the 14th aspects of this invention relate to the seventh, the 10th, and the 11th aspects of this invention, respectively, wherein the nitride film of a metal is comprised by a nitride film of Ti, Ta, Nb, Cr, or a nitride film of an alloy comprised primarily of at least one metal selected from Ti, Ta, Nb, Cr.
These active matrix substrate plates enable to secure reliability of connection at the scanning line terminal section and at the signal line terminal section.
The active matrix substrate plates according to the 15th to the 17th aspects of this invention relate to the 12th to the 14th aspects of this invention, respectively, wherein the nitride film of a metal has a nitrogen concentration of not less than 25 atomic percent.
These active matrix substrate plates enable to secure reliability of connection at the scanning line terminal section and at the signal line terminal section.
The method for manufacturing according to the 18th aspect of this invention is for a TN-type active matrix substrate plate, wherein in a first step, forming a conductor layer on the transparent insulation substrate plate, and excepting the scanning line, a scanning line terminal section formed in a scanning line start end, and in each pixel region, the gate electrode extending from the scanning line to the thin film transistor section or sharing a portion of the scanning line, removing the conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer and an n+ amorphous silicon layer, and excepting the thin film transistor section, removing the semiconductor layer by etching; in a third step, laminating successively on the transparent insulation substrate plate, a transparent conductive layer and a metallic layer, and excepting the signal line, a signal line terminal section formed in the signal line start end section, and in each pixel region, the drain electrode extending from the signal line to the thin film transistor section, the pixel electrode, and the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the metallic layer and the transparent conductive layer by etching, and then removing by etching the n+ amorphous silicon layer where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and after removing the protective insulation layer above the pixel electrode and the signal line terminal section, and the protective insulation layer and the gate insulation layer above the scanning line by etching, removing the metallic layer above the pixel electrode and the signal line terminal section by etching, to expose the pixel electrode and the signal line terminal section comprised by the transparent conductive layer and the scanning line comprised by the conductor layer.
This method enables to manufacture the active matrix substrate plate according to the first aspect of this invention in four steps.
The method for manufacturing according to the 19th aspect of this invention is for an IPS-type active matrix substrate plate, wherein, in a first step, forming a first conductor layer on the transparent insulation substrate plate, and excepting the scanning line, the scanning line terminal section formed in a scanning line start end, and, a common wiring line whose end section at least in one perimeter section of the transparent insulation substrate plate extends outside of an end section of the scanning line in the same perimeter section, a common wiring linking line for connecting end sections of the common wiring line, and in each pixel region, the gate electrode sharing a portion of the scanning line, and a plurality of common electrodes extending from the common wiring line, removing the first conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer and an n+ amorphous silicon layer, and excepting the portion of the scanning line to form the gate electrode for the thin film transistor section in each pixel region, removing the semiconductor layer by etching; in a third step, laminating on the transparent insulation substrate plate a second conductor layer, and excepting the signal line, a signal line terminal section formed in the signal line start end section, and in each pixel region, the drain electrode extending from the signal line above the gate electrode, the pixel electrode opposing the common electrode across the gate insulation layer, and the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the second conductor layer by etching, and then removing by etching the n+ amorphous silicon layer where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and removing the protective insulation layer above the signal line terminal section and the protective insulation layer and the gate insulation layer above the scanning line terminal section and the common wiring line terminal section by etching, to expose the signal line terminal comprised by the second conductor layer and the scanning line terminal comprised by the first conductor layer.
This method of manufacturing an active matrix substrate plate enables to manufacture the active matrix substrate plate according to the second aspect of this invention in four steps.
The method for manufacturing according to the 20th aspect of this invention is for a TN-type active matrix substrate plate, wherein, in a first step, forming a conductor layer on the transparent insulation substrate plate, and excepting the scanning line, a scanning line terminal section formed in a scanning line start end, and in each pixel region, the gate electrode extending from the scanning line to the thin film transistor section or sharing a portion of the scanning line, removing the conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer and an n+ amorphous silicon layer, and a metallic layer, and excepting the signal line or a portion covering the signal line, a signal line terminal section formed on the signal line start end section, and in each pixel region, a protrusion section extending from the signal line to the pixel electrode through the thin film transistor section, removing the metallic layer and the semiconductor layer by etching; in a third step, forming a transparent conductive layer on the transparent insulation substrate plate, and excepting the signal line or the portion covering the signal line, the signal line terminal section formed in the signal line start end section, and in each pixel region, the drain electrode extending from the signal line to the thin film transistor section, the pixel electrode, and the source electrode disposed opposite to the drain electrode across a channel gap, removing the transparent conductive layer by etching, and then removing by etching the metallic layer and the n+ amorphous silicon layer where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and removing the protective insulation layer above the pixel electrode and the signal line terminal section, and the protective insulation layer and the gate insulation layer above the scanning line terminal section by etching, to expose the pixel electrode comprised by the transparent conductive layer, signal line terminal comprised by a lamination of the metallic layer and the transparent conductive layer or the transparent conductive layer itself, and the scanning line terminal comprised by the conductor layer.
This method enables to manufacture the active matrix substrate plate according to the third or the fourth aspect of this invention in four steps.
The method for manufacturing according to the 21st aspect of this invention is for a TN-type active matrix substrate plate, wherein, in a first step, forming a conductor layer on the transparent insulation substrate plate, and excepting the scanning line, a scanning line terminal section formed in a scanning line start end, and in each pixel region, the gate electrode extending from the scanning line to the thin film transistor section or sharing a portion of the scanning line, removing the conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer, and forming an n+ amorphous silicon layer on the semiconductor layer by doping with a group V element, and then depositing a metallic layer, and excepting the signal line or a portion covering the signal line, a signal line terminal section formed on a signal line start end section, and in each pixel region, a protrusion section extending from the signal line to the pixel electrode through the thin film transistor section, removing the metallic layer and the semiconductor layer by etching; in a third step, forming a transparent conductive layer on the transparent insulation substrate plate, and excepting the signal line or the portion covering the signal line, the signal line terminal section formed in the signal line start end section, and in each pixel region, the drain electrode extending from the signal line to the thin film transistor section, the pixel electrode, and the source electrode disposed opposite to the drain electrode across a channel gap, removing the transparent conductive layer by etching, and then removing by etching portions of the metallic layer and the n+ amorphous silicon layer formed by doping with a group V element where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and removing the protective insulation layer above the pixel electrode and the signal line terminal section, and the protective insulation layer and the gate insulation layer above the scanning line terminal section by etching, to expose the pixel electrode comprised by the transparent conductive layer, the signal line terminal comprised by a lamination of the metallic layer and the transparent conductive layer or the transparent conductive layer itself, and the scanning line terminal comprised by the conductor layer.
This method enables to manufacture the active matrix substrate plate according to the fifth aspect of this invention in four steps.
The method for manufacturing according to the 22nd aspect of this invention is for an IPS-type active matrix substrate plate, wherein, in a first step, forming a conductor layer on the transparent insulation substrate plate, and excepting the scanning line, a scanning line terminal section formed in a scanning line start end, and, a common wiring line whose end section at least in one perimeter section of the transparent insulation substrate plate extends outside of an end section of the scanning line in the same perimeter section, a common wiring line linking line for connecting end sections of the common wiring lines, and in each pixel region, the gate electrode sharing a portion of the scanning line, and a plurality of common electrodes extending from the common wiring line, removing the conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer and an n+ amorphous silicon layer, and a metallic layer, and excepting the signal line or the portion covering the signal line, a signal line terminal section formed in the signal line start end section, and in each pixel region, a protrusion section extending from the signal line to the pixel electrode section through the thin film transistor section, removing the metallic layer and the semiconductor layer by etching; in a third step, laminating on the transparent insulation substrate plate a transparent conductive layer or a nitride film layer of a metal or a second metallic layer, and excepting the signal line or the portion covering the signal line, the signal line terminal section formed in the signal line start end section, and in each pixel region, the drain electrode extending from the signal line to the thin film transistor section above the gate electrode, the pixel electrode opposing the common electrode across the gate insulation layer, and the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the transparent conductive layer or the nitride film layer of a metal or the second metallic layer by etching, and then removing by etching portions of the metallic layer and the n+ amorphous silicon layer where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and removing the protective insulation layer above the signal line terminal section and the protective insulation layer and the gate insulation layer above the scanning line terminal section by etching, to expose the signal line terminal comprised by any one of a lamination of the metallic layer and the transparent conductive layer or a nitride film layer of a metal, or the transparent conductive layer, or a nitride film layer of a metal, or the second metallic layer, and the scanning line terminal comprised by the conductor layer.
This method enables to manufacture the active matrix substrate plate according to the second aspect of this invention in four steps.
The method for manufacturing according to the 23rd aspect of this invention is for an IPS-type active matrix, wherein, in a first step, forming a conductor layer on the transparent insulation substrate plate, and excepting the scanning line, a scanning line terminal section formed in a scanning line start end, and, a common wiring line whose end section at least in one perimeter section of the transparent insulation substrate plate extends outside of an end section of the scanning line in the same perimeter section, a common wiring line linking line for connecting end sections of the common wiring lines, and in each pixel region, the gate electrode sharing a portion of the scanning line, and a plurality of common electrodes extending from the common wiring line, removing the conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer, and forming an n+ amorphous silicon layer on the semiconductor layer by doping with a group V element, and then depositing a metallic layer, and excepting the signal line or a portion covering the signal line, a signal line terminal section formed in a signal line start end section, and in each pixel region, a protrusion section extending from the signal line to the pixel electrode section through the thin film transistor section, removing the metallic layer and the semiconductor layer by etching; in a third step, laminating on the transparent insulation substrate plate a transparent conductive layer or a nitride film layer of a metal or a second metallic layer, and excepting the signal line or the portion covering the signal line, the signal line terminal section formed in the signal line start end section, and in each pixel region, the drain electrode extending from the signal line to the thin film transistor section above the gate electrode, the pixel electrode opposing the common electrode across the gate insulation layer, and the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the transparent conductive layer or the nitride film layer of a metal or the second conductor layer by etching, and then removing by etching the metallic layer and the n+ amorphous silicon layer formed by doping with the group V element where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and removing the protective insulation layer above the signal line terminal section, and the protective insulation layer and the gate insulation layer above the scanning line terminal section by etching, to expose the signal line terminal comprised by any one of a lamination of the metallic layer and the transparent conductive layer or a metal nitride film, or the transparent conductive layer, or a metal nitride film layer, or the second metallic layer, and the scanning line terminal comprised by the conductor layer.
This method enables to manufacture the active matrix substrate plate according to the fifth aspect of this invention in four steps.
The method for manufacturing according to the 24th aspect of this invention is for an IPS-type active matrix substrate plate, wherein, in a first step, forming a conductor layer on the transparent insulation substrate plate, and excepting the scanning line, a scanning line terminal section formed in a scanning line start end, and a common wiring line whose end section at least in one perimeter section of the transparent insulation substrate plate extends outside of an end section of the scanning line in the same perimeter section, a common wiring line linking line for connecting end sections of the common wiring lines, and in each pixel region, the gate electrode sharing a portion of the scanning line, and a plurality of common electrodes extending from the common wiring line, removing the conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer and an n+ amorphous silicon layer, and a metallic layer, and excepting the signal line or a portion covering the signal line, a signal line terminal section formed in a signal line start end section, and in each pixel region, a protrusion section extending from the signal line to the pixel electrode section through the thin film transistor section, and the pixel electrode extending from the protrusion section to the common electrode through the gate insulation layer or the portion covering the pixel electrode, removing the metallic layer and the semiconductor layer by etching; in a third step, laminating on the transparent insulation substrate plate a transparent conductive layer or a nitride layer of a metal or a second metallic layer, and excepting the signal line or the portion covering the signal line, the signal line terminal section formed in the signal line start end section, and in each pixel region, the drain electrode extending from the signal line to the thin film transistor section above the gate electrode, the pixel electrode or the portion covering the pixel electrode, and the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the transparent conductive layer or the nitride film layer of a metal or the second metallic layer by etching, and then removing by etching the metallic layer and the n+ amorphous silicon layer where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and removing the protective insulation layer above the signal line terminal section, and the protective insulation layer and the gate insulation layer above the scanning line terminal section by etching, to expose the signal line terminal comprised by any one of a lamination of the metallic layer and the transparent conductive layer or a metal nitride film, or the transparent conductive layer or a metal nitride film layer or the second metallic layer, and the scanning line terminal comprised by the conductor layer.
This method enables to manufacture the active matrix substrate plate according to the second aspect of this invention in four steps.
The method for manufacturing according to the 25th aspect of this invention is for an IPS-type active matrix substrate plate, wherein, in a first step, forming a conductor layer on the transparent insulation substrate plate, and excepting the scanning line, a scanning line terminal section formed in a scanning line start end, and a common wiring line whose end section at least in one perimeter section of the transparent insulation substrate plate extends outside of an end section of the scanning line in the same perimeter section, a common wiring line linking line for connecting end sections of the common wiring lines, and in each pixel region, the gate electrode sharing a portion of the scanning line, and a plurality of common electrodes extending from the common wiring line, removing the conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer, and forming an n+ amorphous silicon layer on the semiconductor layer by doping with a group V element, and then depositing a metallic layer, and excepting the signal line or the portion covering the signal line, a signal line terminal section formed in a signal line start end section, and in each pixel region, a protrusion section extending from the signal line to the pixel electrode section through the thin film transistor section, and the pixel electrode extending from the protrusion section to the opposing common electrode through the gate insulation layer or a portion covering the pixel electrode, removing the metallic layer and the semiconductor layer by etching; in a third step, laminating on the transparent insulation substrate plate a transparent conductive layer or a nitride layer of a metal or a second metallic layer, and excepting the signal line or the portion covering the signal line, the signal line terminal section formed in the signal line start end section, and in each pixel region, the drain electrode extending from the signal line to the thin film transistor section above the gate electrode, the pixel electrode or the portion covering the pixel electrode, and the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the transparent conductive layer or the nitride film layer of a metal or the second metallic layer by etching, and then removing the metallic layer and the n+ amorphous silicon layer formed by doping of the group V element, where expose, by etching; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and removing the protective insulation layer above the signal line terminal section and the protective insulation layer and the gate insulation layer above the scanning line terminal section by etching, to expose the signal line terminal comprised by any one of a lamination of the metallic layer and the transparent conductive layer or a metal nitride film, or the transparent conductive layer or a metal nitride film layer or the second metallic layer, and the scanning line terminal comprised by the conductor layer.
This method enables to manufacture the active matrix substrate plate according to the fifth aspect of this invention in four steps.
The method according to the 26th aspect of this invention relates to manufacturing the active matrix substrate plate according to one of the 18th to the 25th aspects of this invention, wherein in the first step, the conductor layer is formed by laminating Al or an alloy of primarily Al, or by laminating a high melting point metal and an upper layer of Al or an alloy of primarily Al on the transparent insulation substrate plate.
These methods for manufacturing an active matrix substrate plate enables to reduce the wiring resistance of the scanning line and to secure reliability of connection of the scanning line driver at the scanning line terminal section.
The method according to the 27th aspect of this invention relates to manufacturing the active matrix substrate plate according to one of the 18th to the 25th aspects of this invention, wherein in the first step, the conductor layer is formed by laminating not less than one layer of a conductive film and an upper layer of a nitride film of a metal or a transparent conductive film on the transparent insulation substrate plate.
These methods for manufacturing an active matrix substrate plate enables to secure reliability of connection of the scanning line driver at the scanning line terminal section.
The method according to the 28th aspect of this invention relates to manufacturing the active matrix substrate plate according to one of the 19th, the 22nd to the 25th aspects of this invention, wherein in the third step, the second conductor layer or the second metallic layer is formed by laminating a high melting point metal and an upper layer of Al or an alloy of primarily Al.
These methods for manufacturing an active matrix substrate plate enable to reduce the wiring resistance of the signal line and to secure reliability of connection of the signal line driver at the signal line terminal section.
The method according to the 29th aspect of this invention relates to manufacturing the active matrix substrate plate according to the 19th aspect of this invention, wherein, in the third step, the second conductor layer is formed by laminating not less than one layer of a conductive film and an upper layer of a nitride film of a metal or the transparent conductive film.
This method of manufacturing an active matrix substrate plate enables to secure reliability of connection of the signal line driver at the signal line terminal section.
The methods according to the 30th and the 31st aspects of this invention relate to manufacturing the active matrix substrate plate according to the 27th and the 29th aspect of this invention, respectively, wherein the nitride film of a metal is comprised by a nitride film of Ti, Ta, Nb, Cr or a nitride film of an alloy comprised primarily of at least one metal selected from Ti, Ta, Nb, Cr.
This method of manufacturing an active matrix substrate plate enables to secure reliability of connection at the scanning line terminal section and at the signal line terminal section.
The methods according to the 32nd and the 33rd aspects of this invention relate to manufacturing the active matrix substrate plate according to the 30th and the 31st aspects of this invention, respectively, wherein the nitride film of a metal is formed by reactive sputtering so as to produce a nitrogen concentration of not less than 25 atomic percent.
This method of manufacturing an active matrix substrate plate enables to secure reliability of connection at the scanning line terminal and at the signal line terminal in a good condition.
The method according to the 34th aspect of this invention relates to manufacturing the active matrix substrate plate according to one of the first to the fourth aspects of this invention, wherein the signal line is connected to each other by a high resistance line comprised by amorphous silicon.
In this active matrix substrate plate, even if unexpected electrical shock is applied to a signal line during manufacturing processes, because the potential can be dispersed in the adjacent signal lines, it is possible to prevent shorting between the scanning lines and signal lines due to insulation breakdown and to prevent changes in the properties of TFT in the pixel region.
The method according to the 35th aspect of this invention relates to manufacturing the active matrix substrate plate according to one of the first to the fourth aspects of this invention, wherein the signal line is connected to each other across an amorphous silicon layer above a floating electrode formed concurrently with the scanning line.
This active matrix substrate plate has the same benefits as the above substrate plate.
The methods according to the 36th and the 37th aspects of this invention relate to manufacturing the active matrix substrate plate according to one of the 34th and the 35th aspects of this invention, respectively, wherein adjacent signal lines have one pair or a plurality of pairs of opposing protrusion sections in the input side with respect to a pixel region, and the protrusion section is connected to each other by the amorphous silicon layer.
In these active matrix substrate plates, even if unexpected electrical shock is applied to a signal line during manufacturing processes, because the potential can be dispersed in the adjacent signal lines, it is possible to prevent shorting between the scanning lines and signal lines due to insulation breakdown and to prevent changes in the properties of TFT in the pixel region.
The method according to the 38th aspect of this invention relates to manufacturing the active matrix substrate plate according to one of the first to the fourth aspects of this invention, wherein the signal line is connected to a common wiring line by a high resistance line comprised by amorphous silicon.
In these active matrix substrate plates, even if unexpected electrical shock is applied to a signal line during manufacturing processes, because the potential can be dispersed in the common wiring lines, it is possible to prevent shorting between the scanning lines and signal lines due to insulation breakdown and to prevent changes in the properties of TFT in the pixel region.
The method according to the 39th aspect of this invention relates to manufacturing the active matrix substrate plate according to one of the first to the fourth aspects of this invention, wherein the signal line is electrically connected to a common wiring line across an amorphous silicon layer above a floating electrode formed concurrently with the scanning line.
These active matrix substrate plates provide the same beneficial effects as described above.
The methods according to the 40th and the 41st aspects of this invention relate to manufacturing the active matrix substrate plate according to the 38th and the 39th aspects of this invention, respectively, wherein the signal line and the common wiring line formed on the same layer as the signal line, or signal line linking line connected to the common wiring line formed on the same layer as the scanning line and formed on the same layer as the signal line, have one pair or a plurality of pairs of opposing protrusion sections at the signal line end, and the protrusion section is connected to each other by an amorphous silicon layer.
In these active matrix substrate plates, even if unexpected electrical shock is applied to a signal line during manufacturing processes, because the potential can be dispersed in the common wiring lines, it is possible to prevent shorting between the scanning lines and signal lines due to insulation breakdown and to prevent changes in the properties of TFT in the pixel region.
The active matrix substrate plate according to the 42nd aspect of this invention is formed on a transparent insulating substrate plate having an array of pixel regions, wherein each pixel region contains a scanning line and a signal line and is surrounded by the scanning line and the signal line crossing each other at right angles, and in each pixel region is formed an inverted staggered structure thin film transistor comprised by a gate electrode, an island-shaped semiconductor layer opposing the gate electrode across a gate insulation layer, a pair of drain electrode and source electrode separated by a channel gap formed above the semiconductor layer, such that a pixel electrode is formed in a window section surrounded by the scanning line and the signal line for transmitting light, and the gate electrode is connected to the scanning line, the drain electrode is connected to the signal line, and the source electrode is connected to the pixel electrode, wherein, the drain electrode and the source electrode are formed by laminating a metallic layer on top of a transparent conductive layer, and a lamination of the transparent conductive layer and the metallic layer of the source electrode descends vertically to the transparent insulation substrate plate so as to cover a lateral surface of the lamination of the gate insulation layer and the semiconductor layer, and further, the transparent conductive layer below the metallic layer extends on top of the transparent insulation substrate plate towards the window section to form the pixel electrode, and the lateral surface of the conductor layer above the transparent insulation substrate plate formed concurrently with the scanning line is totally covered by the gate insulation layer.
This active matrix substrate plate can be manufactured in four steps so that the productivity and the yield are improved.
Also, in this active matrix substrate plate, because the conductor layer formed together with the scanning line on top of the transparent insulation substrate plate, excepting the connection section to the transparent conductive layer, is totally covered by the gate insulation layer, during etching of metallic layer of the signal line or the transparent conductive layer, corrosion problems of circuit elements such as the scanning lines in the lower layer and gate electrodes or shorting of scanning lines and signal lines are prevented, and the yield is improved.
Also, in this active matrix substrate plate, protective transistor can be fabricated so that the TFT in the pixel region can be prevented from unexpected electrical shock during manufacturing. Also, insulation breakdown between the scanning lines and signal lines can be prevented, and the yield is improved.
Also, in this active matrix substrate plate, because the signal line is formed by laminating a metallic layer and the transparent conductive layer, the wiring resistance of the signal line can be lowered, and also, a drop in yield caused by severing of the signal line can be suppressed, and because the source electrode and the pixel electrode are formed integrally using the transparent conductive layer, an increase in contact resistance can be suppressed and the reliability is improved.
The active matrix substrate plate according to the 43rd aspect of this invention is formed on a transparent insulating substrate plate by a plurality of scanning lines alternating with a plurality of common wiring lines, and a pixel region, containing a scanning line and a signal line is surrounded by the scanning line and the signal line crossing at right angles to each other, is arrayed in such a way that in each pixel region is formed an inverted staggered structure thin film transistor comprised by a gate electrode, an island-shaped semiconductor layer opposing the gate electrode across a gate insulation layer, a pair of drain electrode and source electrode separated by a channel gap formed above the semiconductor layer, such that in a window section surrounded by the scanning line and the signal line are formed a pixel electrode of a comb teeth shape and a common electrode of a comb teeth shape connecting to a common wiring line and opposing the pixel electrode, so that the gate electrode is connected to the scanning line, the drain electrode is connected to the signal line, and the source electrode is connected to the pixel electrode, so as to generate a horizontal electrical field with respect to the transparent insulating substrate plate between the pixel electrode and the common electrode, wherein, the conductor layer of the source electrode descends vertically to the transparent insulation substrate plate so as to cover a lateral surface of a lamination of the gate insulation layer and the semiconductor layer, and further extends on top of the transparent insulation substrate plate towards the window section to form the pixel electrode, and the lateral surface of the conductor layer above the transparent insulation substrate plate formed concurrently with the scanning line is totally covered by the gate insulation layer.
This IPS-type active matrix substrate plate can be manufactured in four steps so that the productivity and the yield are improved.
Also, in this active matrix substrate plate, because the conductor layer formed together with the scanning line on top of the transparent insulation substrate plate, excepting the connection section of the conductor layer above the transparent conductive layer formed concurrently with the scanning line to the conductor layer formed concurrently with the signal line, is totally covered by the gate insulation layer, during etching of conductor layer of the signal line, corrosion problems of circuit elements such as the scanning lines in the lower layer and common wiring or shorting of scanning lines and common wiring and signal lines are prevented, and the yield is improved.
Also, in this active matrix substrate plate, protective transistor can be fabricated so that the TFT in the pixel region can be prevented from unexpected electrical shock during manufacturing. Also, insulation breakdown between the scanning lines and signal lines can be prevented, and the yield is improved
The active matrix substrate plate according to the 44th aspect of this invention is formed on a transparent insulating substrate plate having an array of pixel regions, wherein each pixel region contains a scanning line and a signal line and is surrounded by the scanning line and the signal line crossing each other at right angles, and in each pixel region is formed an inverted staggered structure thin film transistor comprised by a gate electrode, an island-shaped semiconductor layer opposing the gate electrode across a gate insulation layer, a pair of drain electrode and source electrode separated by a channel gap formed above the semiconductor layer, such that a pixel electrode is formed in a window section surrounded by the scanning line and the signal line for transmitting light, and the gate electrode is connected to the scanning line, the drain electrode is connected to the signal line, and the source electrode is connected to the pixel electrode, wherein, the drain electrode and the source electrode are both formed by laminating the transparent conductive layer on top of a metallic layer, and the transparent conductive layer above the source electrode descends vertically to the transparent insulation substrate plate so as to cover a lateral surface of a lamination of the gate insulation layer and the semiconductor layer and the metallic layer, and further extends on top of the transparent insulation substrate plate towards the window section to form the pixel electrode, and the lateral surface of the conductor layer above the transparent insulation substrate plate formed concurrently with the scanning line is totally covered by the gate insulation layer.
This TN-type active matrix substrate plate can be manufactured in four steps so that the productivity and the yield are improved.
Also, in this active matrix substrate plate, because the conductor layer formed together with the scanning line on top of the transparent insulation substrate plate, excepting the connection section to the transparent conductive layer, is totally covered by the gate insulation layer, during etching of metallic layer of the signal line or the transparent conductive layer, corrosion problems of circuit elements such as the scanning lines in the lower layer and gate electrodes or shorting of scanning lines and signal lines are prevented, and the yield is improved.
Also, in this active matrix substrate plate, protective transistor can be fabricated so that the TFT in the pixel region can be prevented from unexpected electrical shock during manufacturing. Also, insulation breakdown between the scanning lines and signal lines can be prevented, and the yield is improved
Also, because the signal line is formed by laminating a metallic layer and the transparent conductive layer, the wiring resistance of the signal line can be lowered, and also, a drop in yield caused by severing of the signal line can be suppressed, and because the source electrode and the pixel electrode are formed integrally using the transparent conductive layer, an increase in contact resistance can be suppressed and the reliability is improved.
The active matrix substrate plate according to the 45th aspect of this invention relates to one according to the 44th aspect of this invention, wherein a thickness of an ohmic contact layer formed in an upper layer of the semiconductor layer formed in a layer below the source electrode and the drain electrode is 3-6 nm.
In this TN-type active matrix substrate plate, in addition to the beneficial effects recited above, when etching the drain and source electrodes, the ohmic contact layer above the semiconductor layer can be etched at the same time, and the thickness of the semiconductor layer can be made thin, so that the productivity is increased and the writing capability of the TFT can be improved.
The active matrix substrate plate according to the 46th aspect of this invention relates to one according to the 43rd aspect of this invention, wherein the signal line is comprised by a lamination of a high melting point metal laminated and an upper layer of Al or an alloy of primarily Al.
This active matrix substrate plate enables to reduce wiring resistance of the signal line and to secure reliability of connection of the signal line driver at the signal line terminal section.
The active matrix substrate plate according to the 47th aspect of this invention relates to one according to the 43rd aspect of this invention, wherein the signal line is comprised by a lamination of conductive films of not less than two layers, and an uppermost layer of the lamination is comprised by a nitride film of a metal or a transparent conductive film.
This active matrix substrate plate enables to secure reliability of connection of the signal line driver at the signal line terminal section.
The active matrix substrate plate according to the 48th aspect of this invention relates to one according to the 47th aspect of this invention, wherein the nitride film of a metal is comprised by a nitride film of Ti, Ta, Nb, Cr or a nitride film of an alloy comprised primarily of at least one metal selected from Ti, Ta, Nb, Cr.
This active matrix substrate plate provides the same beneficial effects as described above.
The active matrix substrate plate according to the 49th aspect of this invention relates to one according to the 48th aspect of this invention, wherein the nitride film of a metal has a nitrogen concentration of not less than 25 atomic percent.
This active matrix substrate plate enables to secure reliability of connection of the signal line driver at the signal line terminal section in a good condition.
The active matrix substrate plate according to the 50th aspect of this invention relates to one according to one of the 42nd to the 45th aspects of this invention, wherein a portion of both lateral surface of the semiconductor layer extending in the direction of the channel gap of the thin film transistor section is covered by the protective insulation layer.
In this active matrix substrate plate, because a portion of both lateral surfaces of the semiconductor layer in the extending direction of the channel gap of the TFT section is covered by the protective insulation layer, it is possible to prevent charge leaking through the lateral surfaces of the semiconductor layer as the current path, thereby improving the reliability of thin film transistors.
The active matrix substrate plate according to the 51st aspect of this invention relates to one according to one of the 42nd to the 45th aspects of this invention, wherein the scanning line is comprised of a conductive film comprised by a lamination of not less than two layers, and an uppermost layer of the lamination serves as an etching protective layer for the conductor layer formed in a lower layer.
These active matrix substrate plates are able to prevent infiltration corrosion caused by the etching solution infiltrating through the opening section punched through the gate insulation layer above the gate electrode and the semiconductor layer, when etching the metallic layer of the signal line or the transparent conductive layer, to corrode the conductor layer in a layer below the gate electrode or the scanning line, thereby improving the yield.
The active matrix substrate plate according to the 52nd aspect of this invention relates to one according to the 51st aspect of this invention, wherein at least one layer of the conductor film in a lower layer is comprised of Al or an alloy of primarily Al, and a conductive film in the uppermost layer is comprised of Ti, Ta, Nb, or an alloy comprised primarily of at least one of preceding elements, or Ti, Ta, Nb, Cr, or a nitride film of an alloy comprised primarily of at least one metal selected from Ti, Ta, Nb, Cr.
This active matrix substrate plate provides the same beneficial effects as described above.
The active matrix substrate plate according to the 53rd aspect of this invention related to one according to one of the 42nd, the 44th and the 45th aspects of this invention, wherein a connection section is formed to connect the first conductor layer where the scanning line is formed and the second conductor layer where the signal line is formed, and the connection section is disposed so as not to superimpose on an opening section of the protective insulation layer.
The active matrix substrate plate according to the 42nd aspect of this invention is constructed so that, even if a same metal is used or different metals are used for the first conductor layer and second conductor layer, if the first conductor layer is not resistant to etching of the metallic layer in the second conductor layer, after the protective insulation layer is opened and when the metal layer above the transparent conductive layer is to be removed by etching, it is possible to prevent the etching solution to infiltrate through the transparent conductive layer at the connection section and corrode the first conductor layer, and the yield is improved.
Also, the active matrix substrate plates according to the 44th and the 45th aspects of this invention are constructed so that, when at least one layer of the first conductor layer is comprised by Al or an alloy of primarily Al, and if a hydrofluoric type acid is used to etch the opening section in the protective insulation layer, during etching operation on the protective insulation layer, it is possible to prevent the etching solution to infiltrate through the transparent conductive layer to corrode Al or an alloy of primarily Al in the first conductor layer, thereby improving the yield.
The active matrix substrate plate according to the 54th aspect of this invention relates to one according to the 42nd or the 43rd aspect of this invention, wherein the first conductor layer where the scanning line is formed and the second conductor layer where the signal line is formed are connected directly through an opening section punched through the gate insulation layer and the semiconductor layer.
These active matrix substrate plates can be manufactured in four steps, because the first conductor layer and the second conductor layer can be electrically connected according to the structure described, so that the productivity and the yield are improved.
Also, in these active matrix substrate plates, protective transistor can be fabricated so that the TFT in the pixel region can be prevented from unexpected electrical shock during manufacturing. Also, insulation breakdown between the scanning lines and signal lines can be prevented, and the yield is improved.
The active matrix substrate plate according to the 55th aspect of this invention relates to one according to the 44th or the 45th aspect of this invention, wherein the first conductor layer where the scanning line is formed and the second conductor layer where the signal line is formed are connected directly the transparent conductive layer through an opening section punched through the gate insulation layer and the semiconductor layer.
These active matrix substrate plates provide the same beneficial effects as described above.
The active matrix substrate plate according to the 56th aspect of this invention relates to one according to the 42nd aspect of this invention, wherein a conductor layer of a forestage scanning line that opposes each other across a lamination comprised by the gate insulation layer and the semiconductor layer and the transparent conductive layer extending from the pixel electrode form an accumulation capacitance section, and in this accumulation capacitance section, lateral end surfaces of the transparent conductive layer and the semiconductor layer are aligned.
This active matrix substrate plate improves productivity and yield because it can be manufactured in four steps due to the structure of the accumulation capacitance section.
The active matrix substrate plate according to the 57th aspect of this invention relates to one according to the 44th or the 45th aspect of this invention, wherein a conductor layer of a forestage scanning line that opposes each other across a lamination comprised by the gate insulation layer and the semiconductor layer and the metallic layer in the pixel region and the transparent conductive layer laminated above form an accumulation capacitance section, and in this accumulation capacitance section, lateral end surfaces of the transparent conductive layer and the metallic layer and the semiconductor layer are aligned.
This active matrix substrate plate provides the same beneficial effects as described above.
The method according to the 58th aspect of this invention relates to manufacturing a TN-type active matrix substrate plate, wherein, in a first step, forming a conductor layer on the transparent insulation substrate plate, and excepting at least the scanning line, a scanning line terminal section formed in a scanning line start end, and in each pixel region, the gate electrode extending from the scanning line to the thin film transistor section or sharing a portion of the scanning line, removing the conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer and an n+ amorphous silicon layer, and excepting a specific opening section formed above the conductor layer in the first step, and leaving so as to cover at least an upper surface of the conductor layer and an entire lateral surface with the gate insulation layer, removing the semiconductor layer and the gate insulation layer by etching; in a third step, laminating successively on the transparent insulation substrate plate, a transparent conductive layer and a metallic layer, and excepting the signal line, a signal line terminal section formed in the signal line terminal location, a connection electrode section connecting to the scanning line terminal section through the opening section formed above the scanning line terminal section, and in each pixel region, the drain electrode extending from the signal line to the thin film transistor section, the pixel electrode, and the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the metallic layer and the transparent conductive layer by etching, and then removing by etching the n+ amorphous silicon layer where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and excepting the protective insulation layer above the pixel electrode and the connection electrode section and the signal line terminal section, and leaving so as to form at least the semiconductor layer of the thin film transistor section, removing the protective insulation layer and the semiconductor layer successively by etching, and then, removing by etching the metallic layer exposed at the opening section formed on the protective insulation layer above the pixel electrode and the connection electrode section and the signal line terminal section to expose the pixel electrode and signal line terminal comprised by the transparent conductive layer, and the scanning line terminal laminated above the conductor layer with the transparent conductive layer through the opening section punched through the semiconductor layer and the gate insulation layer.
This method enables to manufacture the active matrix substrate plate according to the 42nd aspect of this invention in four steps.
The method according to the 59th aspect of this invention relates to manufacturing a TN-type active matrix substrate plate, wherein in a first step, forming a conductor layer on the transparent insulation substrate plate, and excepting at least the scanning line, and in each pixel region, the gate electrode extending from the scanning line to the thin film transistor section or sharing a portion of the scanning line, removing the conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer and an n+ amorphous silicon layer, and excepting a specific opening section formed above the conductor layer in the first step, and leaving so as to cover at least an upper surface of the conductor layer and an entire lateral surface with the gate insulation layer, removing the semiconductor layer and the gate insulation layer by etching; in a third step, laminating successively on the transparent insulation substrate plate, a transparent conductive layer and a metallic layer, and excepting the signal line, a signal line terminal section formed in the signal line terminal location, a connection electrode section connecting to the scanning line end section through the opening section formed above the scanning line end section, a scanning line terminal section formed in a scanning line terminal location by further extending from the connection electrode section, and in each pixel region, the drain electrode extending from the signal line to the thin film transistor section, the pixel electrode, and the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the metallic layer and the transparent conductive layer by etching, and then removing by etching the n+ amorphous silicon layer where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and excepting the protective insulation layer above the pixel electrode and the scanning line terminal section and the signal line terminal section, and leaving so as to form at least the semiconductor layer of the thin film transistor section, removing the protective insulation layer and the semiconductor layer successively by etching, and then, removing the metallic layer exposed at the opening section formed in the protective insulation layer above the pixel electrode and the scanning line terminal section and the signal line terminal section by etching, to expose the pixel electrode and the scanning line terminal and the signal line terminal comprised by the transparent conductive layer.
This method enables to manufacture the active matrix substrate plate according to the 42nd aspect of this invention in four steps.
The method of manufacturing an active matrix substrate plate according to the 60th aspect of this invention relates a TN-type active matrix substrate plate, wherein, in a first step, forming a conductor layer on the transparent insulation substrate plate, and excepting at least the scanning line, a scanning line terminal section formed in a scanning line terminal section location, and in each pixel region, the gate electrode extending from the scanning line to the thin film transistor section or sharing a portion of the scanning line, a lower layer signal line formed non-contactingly between adjacent scanning lines to form a portion of the signal line, removing the conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer and an n+ amorphous silicon layer, and excepting a specific opening section formed above the conductor layer in the first step, and leaving so as to cover at least an upper surface of the conductor layer and an entire lateral surface with the gate insulation layer, removing the semiconductor layer and the gate insulation layer by etching; in a third step, laminating successively on the transparent insulation substrate plate, a transparent conductive layer and a metallic layer, and excepting a signal line terminal section formed in a signal line terminal section location, a connection electrode section connecting to the scanning line terminal section through the opening section formed above the scanning line terminal section, an upper layer signal line connecting the lower layer signal line opposing an adjacent pixel region across the scanning line through an opening section punched through the semiconductor layer and the gate insulation layer, and in each pixel region, the drain electrode extending from the upper layer signal line to the thin film transistor section, the pixel electrode, and the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the metallic layer and the transparent conductive layer by etching, and then removing by etching the n+ amorphous silicon layer where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and excepting the protective insulation layer above the pixel electrode and the connection electrode section and the signal line terminal section, and leaving so as to form at least the semiconductor layer of the thin film transistor section, removing the protective insulation layer and the semiconductor layer successively by etching, and then, removing the metallic layer exposed at the opening section formed in the protective insulation layer above the pixel electrode and the connection electrode section and the signal line terminal section by etching, to expose the signal line terminal and the pixel electrode comprised by the transparent conductive layer, and the scanning line terminal laminated above the conductor layer with the transparent conductive layer through the opening section punched through the semiconductor layer and the gate insulation layer.
This method enables to manufacture the active matrix substrate plate according to the 42nd aspect of this invention in four steps.
The method of manufacturing an active matrix substrate plate according to the 61st aspect of this invention relates to a TN-type active matrix substrate plate, wherein, in a first step, forming a conductor layer on the transparent insulation substrate plate, and excepting at least the scanning line, and in each pixel region, the gate electrode extending from the scanning line to the thin film transistor section or sharing a portion of the scanning line, a lower layer signal line formed non-contactingly between adjacent scanning lines to form a portion of the signal line, removing the conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer and an n+ amorphous silicon layer, and excepting a specific opening section formed above the conductor layer in the first step, and leaving so as to cover at least an upper surface of the conductor layer and an entire lateral surface with the gate insulation layer, removing the semiconductor layer and the gate insulation layer by etching; in a third step, laminating successively on the transparent insulation substrate plate, a transparent conductive layer and a metallic layer, and excepting a signal line terminal section formed in a signal line terminal section location, a connection electrode section connecting to the scanning line end section through the opening section formed above the scanning line end section, the scanning line terminal section formed in the scanning line terminal section location by further extending from the connection electrode section, an upper layer signal line connecting to the lower layer signal line opposing an adjacent pixel region across the scanning line through an opening section punched through the semiconductor layer and the gate insulation layer, and in each pixel region, the drain electrode extending from the upper layer signal line to the thin film transistor section, the pixel electrode, and the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the metallic layer and the transparent conductive layer by etching, and then removing by etching the n+ amorphous silicon layer where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and excepting the protective insulation layer above the pixel electrode and the scanning line terminal section and the signal line terminal section, and leaving so as to form at least the semiconductor layer of the thin film transistor section, removing the protective insulation layer and the semiconductor layer are successively by etching, and then, removing the metallic layer exposed at the opening section formed in the protective insulation layer above the pixel electrode and the scanning line terminal section and the signal line terminal section by etching, to expose the signal line terminal and the scanning line terminal and the pixel electrode comprised by the transparent conductive layer.
This method enables to manufacture the active matrix substrate plate according to the 42nd aspect of this invention in four steps.
The method for manufacturing an active matrix substrate plate according to the 62nd aspect of this invention relates to an IPS-type active matrix substrate plate, wherein, in a first step, forming a first conductor layer on the transparent insulation substrate plate, and excepting at least the scanning line, a scanning line terminal section formed in a scanning line terminal section location, and the common wiring line, and in each pixel region, the gate electrode sharing a portion of the scanning line, removing the first conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and the semiconductor layer comprised by an amorphous silicon layer and an n+ amorphous silicon layer, and excepting a specific opening section above the first conductor layer pattern formed in the first step, and leaving so as to cover at least an upper surface of the first conductor layer and an entire lateral surface with a semiconductor layer and the gate insulation layer, removing the semiconductor layer and the gate insulation layer by etching; in a third step, laminating on the transparent insulation substrate plate a second conductor layer, and excepting the signal line, a signal line terminal section formed in a signal line terminal section location, a connection electrode section connecting to the scanning line terminal section through the opening section formed above the scanning line terminal section, a common wiring linking line connecting to the opening section formed above the end section of the common wiring line to electrically connect the end section of the common wiring line, a common wiring line terminal section connecting to the common wiring linking line, and in each pixel region, the drain electrode extending from the signal line to the thin film transistor section, and in each pixel region, the pixel electrode extending from the signal line to the gate electrode section, a plurality of common electrodes whose base sections are connected to the common wiring line through the opening section punched through the semiconductor layer and the gate insulation layer, the pixel electrode extending so as to be clamped by the common electrodes, the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the second conductor layer by etching, and then removing by etching the n+ amorphous silicon layer where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and excepting the protective insulation layer above the connection electrode section and the signal line terminal section and the common wiring line terminal section, and leaving to form at least the semiconductor layer of the thin film transistor, removing protective insulation layer and the semiconductor layer by etching, to expose the scanning line terminal laminated with the second conductor layer through the opening section punched through the semiconductor layer and the gate insulation layer above the first conductor layer, and the signal line terminal and the common wiring line terminal comprised by the second conductor layer.
This method enables to manufacture the active matrix substrate plate according to the 43rd aspect of this invention in four steps.
The method for manufacturing an active matrix substrate plate according to the 63rd aspect of this invention relates to an IPS-type active matrix substrate plate, wherein, in a first step, forming a first conductor layer on the transparent insulation substrate plate, and excepting at least the scanning line, the common wiring line, and in each pixel region, the gate electrode sharing a portion of the scanning line, removing the first conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer and an n+ amorphous silicon layer, and excepting a specific opening section above the first conductor layer pattern formed in the first step, and leaving so as to cover at least an upper surface of the first conductor layer and an entire lateral surface with a semiconductor layer and the gate insulation layer, removing the semiconductor layer and the gate insulation layer by etching; in a third step, laminating on the transparent insulation substrate plate a second conductor layer, and excepting the signal line, a signal line terminal section formed in a signal line terminal section location, a connection electrode section connecting to the scanning line end section through the opening section formed above the scanning line end section, a scanning line terminal section formed by further extending from the connection electrode section, a common wiring linking line connecting to the end section of the common wiring line through the opening section formed above the end section of the common wiring line to electrically connect the end section of the common wiring line, a common wiring line terminal section connecting to the common wiring linking line, and in each pixel region, the drain electrode extending from the signal line to the thin film transistor section formed on the scanning line, a plurality of common electrodes whose base sections are connected to the common wiring line through the opening section punched through the semiconductor layer and the gate insulation layer, the pixel electrode extending so as to be clamped by the common electrodes, the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the second conductor layer by etching, and then removing by etching the n+ amorphous silicon layer where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and excepting the protective insulation layer above the signal line terminal section and the scanning line terminal section and the common wiring line terminal section, and leaving to form at least the semiconductor layer of the thin film transistor, removing the protective insulation layer and the semiconductor layer by etching, to expose the scanning line terminal and the signal line terminal and common wiring line terminal comprised by the second conductor layer.
This method enables to manufacture the active matrix substrate plate according to the 43rd aspect of this invention in four steps.
The method for manufacturing an active matrix substrate plate according to the 64th aspect of this invention relates to an IPS-type active matrix substrate plate, wherein in a first step, forming a first conductor layer on the transparent insulation substrate plate, and excepting at least the scanning line, a scanning line terminal section formed in a scanning line terminal section location, and the common wiring line, and in each pixel region, the gate electrode sharing a portion of the scanning line, a plurality of common electrodes extending from the common wiring line, removing the first conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer and an n+ amorphous silicon layer, and excepting a specific opening section above the first conductor layer pattern formed in the first step, and leaving so as to cover at least an upper surface and an entire lateral surface of the first conductor layer with the semiconductor layer and the gate insulation layer, removing the semiconductor layer and the gate insulation layer by etching; in a third step, laminating on the transparent insulation substrate plate a second conductor layer, and excepting the signal line, a signal line terminal section formed in a signal line terminal section location, a connection electrode section connecting to the scanning line terminal section through the opening section formed above the scanning line terminal section, a common wiring linking line connecting to the end section of the common wiring line through the opening section formed above the end section of the common wiring line to electrically connect the end section of the common wiring line, a common wiring line terminal section connecting to the common wiring linking line, and in each pixel region, the drain electrode extending from the signal line to the thin film transistor section, and in each pixel region, the pixel electrode extending from the signal line to the gate electrode section, the pixel electrode extending opposite to the common electrode, the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the second conductor layer by etching, and then removing by etching the n+ amorphous silicon layer where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and excepting the protective insulation layer above the connection electrode section and the signal line terminal section and the common wiring line terminal section, and leaving to form at least the semiconductor layer of the thin film transistor, removing the protective insulation layer and the semiconductor layer by etching, to expose the scanning line terminal laminated with the second conductor layer through the opening section punched through the semiconductor layer and the gate insulation layer above the first conductor layer, and the signal line terminal and the common wiring line terminal comprised by the second conductor layer.
This method enables to manufacture the active matrix substrate plate according to the 43rd aspect of this invention in four steps.
The method for manufacturing an active matrix substrate plate according to the 65th aspect of this invention relates to an IPS-type active matrix substrate plate, in a first step, forming a first conductor layer on the transparent insulation substrate plate, and excepting the scanning line, the common wiring line, the gate electrode sharing a portion of the scanning line, a plurality of common electrodes extending from the common wiring line, removing the first conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer and an n+ amorphous silicon layer, and excepting a specific opening section above the first conductor layer pattern formed in the first step, and leaving so as to cover at least an upper surface of the first conductor layer and an entire lateral surface with the semiconductor layer and the gate insulation layer, removing the semiconductor layer and the gate insulation layer by etching; in a third step, laminating on the transparent insulation substrate plate a second conductor layer, and excepting the signal line, a signal line terminal section formed in a signal line terminal section location, a connection electrode section connecting to the scanning line end section through the opening section formed above the scanning line end section, a scanning line terminal section formed by further extending from the connection electrode section, a common wiring linking line connecting to the end section of the common wiring line through the opening section formed above the end section of the common wiring line to electrically connect the end section of the common wiring line, a common wiring line terminal section connecting to the common wiring linking line, and in each pixel region, the drain electrode extending from the signal line to the thin film transistor section, the pixel electrode extending from the signal line to the gate electrode section, the pixel electrode extending so as to be clamped by the common electrode, the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the second conductor layer by etching, and then removing by etching the n+ amorphous silicon layer where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and after removing the protective insulation layer above the connection electrode section and the signal line terminal section and the common wiring line terminal section, and leaving so as to form at least the semiconductor layer of the thin film transistor, removing the protective insulation layer and the semiconductor layer by etching, to expose the scanning line terminal and the signal line terminal and the common wiring line terminal comprised by the second conductor layer.
This method enables to manufacture the active matrix substrate plate according to the 43rd aspect of this invention in four steps.
The method of manufacturing an active matrix substrate plate according to the 66th aspect of this invention relates to forming on a transparent insulating substrate plate having an array of pixel regions, wherein each pixel region contains a scanning line and a signal line and is surrounded by the scanning line and the signal line crossing each other at right angles, and in each pixel region is formed an inverted staggered structure thin film transistor comprised by a gate electrode, an island-shaped semiconductor layer opposing the gate electrode across a gate insulation layer, a pair of drain electrode and source electrode separated by a channel gap formed above the semiconductor layer, such that a pixel electrode is formed in a window section surrounded by the scanning line and the signal line for transmitting light, and the gate electrode is connected to the scanning line, the drain electrode is connected to the signal line, and the source electrode is connected to the pixel electrode, the method comprising: in a first step, forming a conductor layer on the transparent insulation substrate plate, and excepting at least the scanning line, a scanning line terminal section formed in a scanning line terminal section location, and in each pixel region, the gate electrode extending from the scanning line to the thin film transistor section or sharing a portion of the scanning line, removing the conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer and an n+ amorphous silicon layer and a metallic layer, and removing by etching at least a specific opening section above the conductor layer pattern formed in the first step and the metallic layer and the semiconductor layer and the gate insulation layer where the pixel electrode is to be formed; in a third step, forming a transparent conductive layer on the transparent insulation substrate plate, and excepting the signal line, a signal line terminal section formed in a signal line terminal section location, a connection electrode section connecting to the scanning line terminal section through the opening section formed above the scanning line terminal section, and in each pixel region, the drain electrode extending from the signal line to the thin film transistor section, the pixel electrode, and the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the transparent conductive layer by etching, and then removing by etching the metal layer and the n+ amorphous silicon layer where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and excepting the protective insulation layer above the pixel electrode and the connection electrode section and the signal line terminal section, and leaving so as to cover at least an upper surface and an entire lateral surface of the signal line with the protective insulation layer and so as to form the semiconductor layer of the thin film transistor, removing successively the protective insulation layer and the semiconductor layer by etching, to expose the pixel electrode comprised by the transparent conductive layer, the signal line terminal comprised by a lamination of the metallic layer and the transparent conductive layer or the transparent conductive layer itself, the scanning line terminal laminated above the conductor layer with the transparent conductive layer through the opening punched through the semiconductor layer and the gate insulation layer.
This method enables to manufacture the active matrix substrate plate according to the 44th aspect of this invention in four steps.
The method of manufacturing an active matrix substrate plate according to the 67th aspect of this invention relates to forming on a transparent insulating substrate plate having an array of pixel regions, wherein each pixel region contains a scanning line and a signal line and is surrounded by the scanning line and the signal line crossing each other at right angles, and in each pixel region is formed an inverted staggered structure thin film transistor comprised by a gate electrode, an island-shaped semiconductor layer opposing the gate electrode across a gate insulation layer, a pair of drain electrode and source electrode separated by a channel gap formed above the semiconductor layer, such that a pixel electrode is formed in a window section surrounded by the scanning line and the signal line for transmitting light, and the gate electrode is connected to the scanning line, the drain electrode is connected to the signal line, and the source electrode is connected to the pixel electrode, the method comprising: in a first step, forming a conductor layer on the transparent insulation substrate plate, and excepting at least the scanning line, and in each pixel region, the gate electrode extending from the scanning line to the thin film transistor section or sharing a portion of the scanning line, removing the conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer and an n+ amorphous silicon layer, and a metallic layer, and removing by etching at least a specific opening section above the conductor layer pattern formed in the first step and the metallic layer and the semiconductor layer and the gate insulation layer where the pixel electrode is to be formed; in a third step, forming a transparent conductive layer on the transparent insulation substrate plate, and excepting the signal line, a signal line terminal section formed in a signal line terminal section location, a connection electrode section connecting to the scanning line end section through the opening section formed above the scanning line end section, a scanning line terminal section formed by further extending from the connection electrode section, and in each pixel region, the drain electrode extending from the signal line to the thin film transistor section, the pixel electrode, and the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the transparent conductive layer by etching, and then removing by etching the metal layer and the n+ amorphous silicon layer where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and excepting the protective insulation layer above the pixel electrode and the scanning line terminal section and the signal line terminal section, and leaving so as to cover at least an upper surface and an entire lateral surface of the signal line with the protective insulation layer and so as to form the semiconductor layer of the thin film transistor, removing successively the protective insulation layer and the semiconductor layer by etching, to expose the pixel electrode comprised by the transparent conductive layer, and the scanning line terminal and the signal line terminal comprised by a lamination of the metallic layer and the transparent conductive layer or the transparent conductive layer itself.
This method enables to manufacture the active matrix substrate plate according to the 44th aspect of this invention in four steps.
The method of manufacturing an active matrix substrate plate according to the 68th aspect of this invention relates to forming on a transparent insulating substrate plate having an array of pixel regions, wherein each pixel region contains a scanning line and a signal line and is surrounded by the scanning line and the signal line crossing each other at right angles, and in each pixel region is formed an inverted staggered structure thin film transistor comprised by a gate electrode, an island-shaped semiconductor layer opposing the gate electrode across a gate insulation layer, a pair of drain electrode and source electrode separated by a channel gap formed above the semiconductor layer, such that a pixel electrode is formed in a window section surrounded by the scanning line and the signal line for transmitting light, and the gate electrode is connected to the scanning line, the drain electrode is connected to the signal line, and the source electrode is connected to the pixel electrode, the method comprising: in a first step, forming a conductor layer on the transparent insulation substrate plate, and excepting at least the scanning line, the scanning line terminal section formed in a scanning line terminal section location, a lower layer signal line formed non-contactingly between adjacent scanning lines to form a portion of the signal line, and in each pixel region, the gate electrode extending from the scanning line to the thin film transistor section or sharing a portion of the scanning line, removing the conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer and an n+ amorphous silicon layer and a metallic layer, and removing by etching at least a specific opening section above the conductor layer pattern formed in the first step and the metallic layer and the semiconductor layer and the gate insulation layer where the pixel electrode is to be formed; in a third step, forming a transparent conductive layer on the transparent insulation substrate plate, and excepting an upper layer signal line connecting to a lower layer signal line opposing an adjacent pixel region across the scanning line through an opening section punched through the semiconductor layer and the gate insulation layer, a signal line terminal section formed in a signal line terminal section location, a connection electrode section connecting to the scanning line terminal section through the opening section formed above the scanning line terminal section, and in each pixel region, the drain electrode extending from the upper layer signal line to the thin film transistor section, the pixel electrode, and the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the transparent conductive layer by etching, and then removing by etching the metal layer and the n+ amorphous silicon layer where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and excepting the protective insulation layer above the pixel electrode and the connection electrode section and the signal line terminal section, and leaving so as to cover at least an upper surface and an entire lateral surface of the upper layer signal line with the protective insulation layer and so as to form the semiconductor layer of the thin film transistor, removing successively the protective insulation layer and the semiconductor layer by etching, to expose the pixel electrode comprised by the transparent conductive layer, the signal line terminal comprised by a lamination of the metallic layer and the transparent conductive layer or the transparent conductive layer itself, scanning line terminal laminated above the conductor layer with the transparent conductive layer through the opening section punched through the semiconductor layer and the gate insulation layer.
This method enables to manufacture the active matrix substrate plate according to the 44th aspect of this invention in four steps.
The method of manufacturing an active matrix substrate plate according to the 69th aspect of this invention relates to forming on a transparent insulating substrate plate having an array of pixel regions, wherein each pixel region contains a scanning line and a signal line and is surrounded by the scanning line and the signal line crossing each other at right angles, and in each pixel region is formed an inverted staggered structure thin film transistor comprised by a gate electrode, an island-shaped semiconductor layer opposing the gate electrode across a gate insulation layer, a pair of drain electrode and source electrode separated by a channel gap formed above the semiconductor layer, such that a pixel electrode is formed in a window section surrounded by the scanning line and the signal line for transmitting light, and the gate electrode is connected to the scanning line, the drain electrode is connected to the signal line, and the source electrode is connected to the pixel electrode, the method comprising: in a first step, forming a conductor layer on the transparent insulation substrate plate, and excepting at least the scanning line, a lower layer signal line formed non-contactingly between adjacent scanning lines to form a portion of the signal line, and in each pixel region, the gate electrode extending from the scanning line to the thin film transistor section or sharing a portion of the scanning line, removing the conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer and an n+ amorphous silicon layer and a metallic layer, and removing by etching at least a specific opening section above the conductor layer pattern formed in the first step and the metallic layer and the semiconductor layer and the gate insulation layer where the pixel electrode is to be formed; in a third step, forming a transparent conductive layer on the transparent insulation substrate plate, and excepting an upper layer signal line connecting to a lower layer signal line opposing an adjacent pixel region across the scanning line through an opening section punched through the semiconductor layer and the gate insulation layer, a signal line terminal section formed in a signal line terminal section location, a connection electrode section connecting to the scanning line end section through the opening section formed above the scanning line end section, a scanning line terminal section formed by further extending from the connection electrode section, and in each pixel region, the drain electrode extending from the upper layer signal line to the thin film transistor section, the pixel electrode, and the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the transparent conductive layer by etching, and then removing by etching the metal layer and the n+ amorphous silicon layer where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and excepting the protective insulation layer above the pixel electrode and the scanning line terminal section and the signal line terminal section, and leaving so as to cover at least an upper surface and an entire lateral surface of the upper layer signal line with the protective insulation layer and so as to form the semiconductor layer of the thin film transistor, removing successively the protective insulation layer and the semiconductor layer by etching, to expose the pixel electrode comprised by the transparent conductive layer, the scanning line terminal and the signal line terminal comprised by a lamination of the metallic layer and the transparent conductive layer or the transparent conductive layer itself.
This method enables to manufacture the active matrix substrate plate according to the 44th aspect of this invention in four steps.
The method of manufacturing an active matrix substrate plate according to the 70th aspect of this invention relates to forming on a transparent insulating substrate plate having an array of pixel regions, wherein each pixel region contains a scanning line and a signal line and is surrounded by the scanning line and the signal line crossing each other at right angles, and in each pixel region is formed an inverted staggered structure thin film transistor comprised by a gate electrode, an island-shaped semiconductor layer opposing the gate electrode across a gate insulation layer, a pair of drain electrode and source electrode separated by a channel gap formed above the semiconductor layer, such that a pixel electrode is formed in a window section surrounded by the scanning line and the signal line for transmitting light, and the gate electrode is connected to the scanning line, the drain electrode is connected to the signal line, and the source electrode is connected to the pixel electrode, the method comprising: in a first step, forming a conductor layer on the transparent insulation substrate plate, and excepting at least the scanning line, a scanning line terminal section formed in a scanning line terminal section location, and in each pixel region, the gate electrode extending from the scanning line to the thin film transistor section or sharing a portion of the scanning line, removing the conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer, and forming an n+ amorphous silicon layer on the semiconductor layer by doping with a group V element, and then depositing a metallic layer, and removing by etching at least a specific opening section above the conductor layer pattern formed in the first step, the portion of the metallic layer and the semiconductor layer and the gate insulation layer where the pixel electrode is to be formed; in a third step, forming a transparent conductive layer on the transparent insulation substrate plate, and excepting the signal line, a signal line terminal section formed in a signal line terminal section location, a connection electrode section connecting to the scanning line terminal section through the opening section formed above the scanning line terminal section, and in each pixel region, the drain electrode extending from the signal line to the thin film transistor section, the pixel electrode, and the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the transparent conductive layer by etching, and then removing by etching the metal layer and the n+ amorphous silicon layer formed by doping with a group V element where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and excepting the protective insulation layer above the pixel electrode and the connection electrode section and the signal line terminal section, and leaving so as to cover at least an upper surface and an entire lateral surface of the signal line with the protective insulation layer and so as to form the semiconductor layer of the thin film transistor, removing successively the protective insulation layer and the semiconductor layer by etching, to expose the pixel electrode comprised by the transparent conductive layer, the signal line terminal comprised by a lamination of the metallic layer and the transparent conductive layer or the transparent conductive layer itself, the scanning line terminal laminated above the conductor layer with the transparent conductive layer through the opening section punched through the semiconductor layer and the gate insulation layer.
This method enables to manufacture the active matrix substrate plate according to the 45th aspect of this invention in four steps.
The method of manufacturing an active matrix substrate plate according to the 71st aspect of this invention relates to forming on a transparent insulating substrate plate having an array of pixel regions, wherein each pixel region contains a scanning line and a signal line and is surrounded by the scanning line and the signal line crossing each other at right angles, and in each pixel region is formed an inverted staggered structure thin film transistor comprised by a gate electrode, an island-shaped semiconductor layer opposing the gate electrode across a gate insulation layer, a pair of drain electrode and source electrode separated by a channel gap formed above the semiconductor layer, such that a pixel electrode is formed in a window section surrounded by the scanning line and the signal line for transmitting light, and the gate electrode is connected to the scanning line, the drain electrode is connected to the signal line, and the source electrode is connected to the pixel electrode, the method comprising: in a first step, forming a conductor layer on the transparent insulation substrate plate, and excepting at least the scanning line, and in each pixel region, the gate electrode extending from the scanning line to the thin film transistor section or sharing a portion of the scanning line, removing the conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer, and forming an n+ amorphous silicon layer on the semiconductor layer by doping with a group V element, and then depositing a metallic layer, and removing by etching a specific opening section above the conductor layer pattern formed in the first step, the portion of the metallic layer and the semiconductor layer and the gate insulation layer where the pixel electrode is to be formed; in a third step, forming a transparent conductive layer on the transparent insulation substrate plate, and excepting the signal line, the signal line end section formed in the signal line end section location, the connection electrode section connecting to the scanning line end section through the opening section formed above the scanning line end section, a scanning line terminal section formed by further extending from the connection electrode section, and in each pixel region, the drain electrode extending from the signal line to the thin film transistor section, the pixel electrode, and the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the transparent conductive layer by etching, and then removing by etching the metal layer and the n+ amorphous silicon layer formed by doping with a group V element where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and excepting the protective insulation layer above the pixel electrode and the scanning line terminal section and the signal line terminal section, and leaving so as to cover at least an upper surface and an entire lateral surface of the signal line with the protective insulation layer and so as to form the semiconductor layer of the thin film transistor, removing successively the protective insulation layer and the semiconductor layer by etching, to expose the pixel electrode comprised by the transparent conductive layer, the scanning line terminal and the signal line terminal comprised by a lamination of the metallic layer and the transparent conductive layer or the transparent conductive layer itself.
This method enables to manufacture the active matrix substrate plate according to the 45th aspect of this invention in four steps.
The method of manufacturing an active matrix substrate plate according to the 72nd aspect of this invention relates to forming on a transparent insulating substrate plate having an array of pixel regions, wherein each pixel region contains a scanning line and a signal line and is surrounded by the scanning line and the signal line crossing each other at right angles, and in each pixel region is formed an inverted staggered structure thin film transistor comprised by a gate electrode, an island-shaped semiconductor layer opposing the gate electrode across a gate insulation layer, a pair of drain electrode and source electrode separated by a channel gap formed above the semiconductor layer, such that a pixel electrode is formed in a window section surrounded by the scanning line and the signal line for transmitting light, and the gate electrode is connected to the scanning line, the drain electrode is connected to the signal line, and the source electrode is connected to the pixel electrode, the method comprising: in a first step, forming a conductor layer on the transparent insulation substrate plate, and excepting at least the scanning line, a scanning line terminal section formed in a scanning line terminal section location, a lower layer signal line formed non-contactingly between adjacent scanning lines to form a portion of the signal line, and in each pixel region, the gate electrode extending from the scanning line to the thin film transistor section or sharing a portion of the scanning line, removing the conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer, and forming an n+ amorphous silicon layer on the semiconductor layer by doping with a group V element, and then depositing a metallic layer, and removing by etching at least a specific opening section above the conductor layer pattern formed in the first step, the portion of the metallic layer and the semiconductor layer and the gate insulation layer where the pixel electrode is to be formed; in a third step, forming a transparent conductive layer on the transparent insulation substrate plate, and excepting an upper layer signal line connecting to a lower layer signal line opposing an adjacent pixel region across the scanning line through an opening section punched through the semiconductor layer and the gate insulation layer, a signal line terminal section formed in a signal line terminal section location, a connection electrode section connecting to the scanning line terminal section through the opening section formed above the scanning line terminal section, and in each pixel region, the drain electrode extending from the upper layer signal line to the thin film transistor section, the pixel electrode, and the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the transparent conductive layer by etching, and then removing by etching the metal layer and the n+ amorphous silicon layer formed by doping with the group V element where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and excepting the protective insulation layer above the pixel electrode and the connection electrode section and the signal line terminal section, and leaving so as to cover at least an upper surface and an entire lateral surface of the upper layer signal line with the protective insulation layer and so as to form the semiconductor layer of the thin film transistor, removing successively the protective insulation layer and the semiconductor layer by etching, to expose the pixel electrode comprised by the transparent conductive layer, the signal line terminal comprised by a lamination of the metallic layer and the transparent conductive layer or the transparent conductive layer itself, the scanning line terminal laminated above the conductor layer with the transparent conductive layer through the opening section punched through the semiconductor layer and the gate insulation layer.
This method enables to manufacture the active matrix substrate plate according to the 45th aspect of this invention in four steps.
The method of manufacturing an active matrix substrate plate according to the 73rd aspect of this invention relates to forming on a transparent insulating substrate plate having an array of pixel regions, wherein each pixel region contains a scanning line and a signal line and is surrounded by the scanning line and the signal line crossing each other at right angles, and in each pixel region is formed an inverted staggered structure thin film transistor comprised by a gate electrode, an island-shaped semiconductor layer opposing the gate electrode across a gate insulation layer, a pair of drain electrode and source electrode separated by a channel gap formed above the semiconductor layer, such that a pixel electrode is formed in a window section surrounded by the scanning line and the signal line for transmitting light, and the gate electrode is connected to the scanning line, the drain electrode is connected to the signal line, and the source electrode is connected to the pixel electrode, the method comprising: in a first step, forming a conductor layer on the transparent insulation substrate plate, and excepting at least the scanning line, a lower layer signal line formed non-contactingly between adjacent scanning lines to form a portion of the signal line, and in each pixel region, the gate electrode extending from the scanning line to the thin film transistor section or sharing a portion of the scanning line, removing the conductor layer by etching; in a second step, laminating successively on the transparent insulation substrate plate, a gate insulation layer and a semiconductor layer comprised by an amorphous silicon layer, and forming an n+ amorphous silicon layer on the semiconductor layer by doping with a group V element, and then depositing a metallic layer, and removing by etching at least a specific opening section above the conductor layer pattern formed in the first step, the portion of the metallic layer and the semiconductor layer and the gate insulation layer where the pixel electrode is to be formed; in a third step, forming a transparent conductive layer on the transparent insulation substrate plate, and excepting an upper layer signal line connecting to a lower layer signal line opposing an adjacent pixel region across the scanning line through an opening section punched through the semiconductor layer and the gate insulation layer, a signal line terminal section formed in a signal line terminal section location, a connection electrode section connecting to the scanning line end section through the opening section formed above the scanning line end section, a scanning line terminal section formed by further extending from the connection electrode section, and in each pixel region, the drain electrode extending from the upper layer signal line to the thin film transistor section, the pixel electrode, and the source electrode extending from the pixel electrode to the thin film transistor section disposed opposite to the drain electrode across a channel gap, removing the transparent conductive layer by etching, and then removing by etching the metal layer and the n+ amorphous silicon layer formed by doping of the group V element where exposed; and in a fourth step, forming a protective insulation layer on the transparent insulation substrate plate, and excepting the protective insulation layer above the pixel electrode and the scanning line terminal section and the signal line terminal section, and leaving so as to cover at least an upper surface and an entire lateral surface of the upper layer signal line with the protective insulation layer and so as to form the semiconductor layer of the thin film transistor, removing successively the protective insulation layer and the semiconductor layer by etching, to expose the pixel electrode comprised by the transparent conductive layer, the scanning line terminal and the signal line terminal comprised by a lamination of the metallic layer and the transparent conductive layer or the transparent conductive layer itself.
This method enables to manufacture the active matrix substrate plate according to the 45th aspect of this invention in four steps.
The method of manufacturing an active matrix substrate plate according to the 74th aspect of this invention relates to one according to one of the 62nd to the 65th aspects of this invention, wherein in the third step, the second conductor layer is formed by laminating a high melting point metal and an upper layer of Al or an alloy of primarily Al.
This method for manufacturing this active matrix substrate plate enables to lower the wiring resistance of signal line and to secure reliability of connection of the signal line driver at the signal line terminal section. When the structure of the scanning line terminal is the same as that for the signal line terminal, reliability of connection of the scanning line driver at the scanning line terminal section can similarly be secured.
The method of manufacturing an active matrix substrate plate according to the 75th aspect of this invention related to one according to one of the 62nd to the 65th aspects of this invention, wherein, in the third step, the second conductor layer is formed by laminating not less than one layer of a conductive film and an upper layer of a nitride film of a metal or a transparent conductive layer.
This method for manufacturing these active matrix substrate plates enables to secure reliability of connection of the signal line driver at the signal line terminal section. When the structure of the scanning line terminal is the same as that for the signal line terminal, reliability of connection of the scanning line driver at the scanning line terminal can similarly be secured.
A method of manufacturing an active matrix substrate plate according to the 76th aspect of this invention relates to the 75th aspect of this invention, wherein the nitride film of a metal is comprised by a nitride film of Ti, Ta, Nb, Cr or a nitride film of an alloy comprised primarily of at least one metal selected from Ti, Ta, Nb, Cr.
This method for manufacturing an active matrix substrate plate provides the same beneficial effects as described above.
The method of manufacturing an active matrix substrate plate according to the 77th aspect of this invention relates to the 76th aspect of this invention, wherein the nitride film of a metal is formed by reactive sputtering so as to produce a nitrogen concentration of not less than 25 atomic percent.
This method for manufacturing an active matrix substrate plate enables to secure good reliability of connection of the signal line driver at the signal line terminal section. When the structure of the scanning line terminal is the same as that for the signal line terminal, reliability of connection of the scanning line driver at the scanning line terminal can similarly be secured.
The method of manufacturing an active matrix substrate plate according to the 78th aspect of this invention relates to the 18th aspect of this invention, wherein, on the outside of a display surface where the pixel regions are arranged in a matrix, a gate-shunt bus line is formed for connecting the respective scanning line, and on the outside of the display surface, a drain-shunt bus line is formed for connecting the respective signal line, and the gate-shunt bus line and the drain-shunt bus line are connected at least at one point, and when manufacturing the active matrix substrate plate, in the first step, excepting the gate-shunt bus line for connecting respective scanning line, removing the conductor layer by etching; in the third step, leaving so as to superimpose the drain-shunt bus line for connecting respective signal line on the gate-shunt bus line at one point at least and removing the metallic layer and the transparent conductive layer by etching; and in the fourth step, removing by etching the protective insulation layer and the metallic layer above a superposition location of the gate-shunt bus line and the drain-shunt bus line, and irradiating the superposition location with a laser beam to fuse and short circuit the gate-shunt bus line and the drain-shunt bus line by punching through the gate insulation layer.
This method allows easily fusing of the gate-shunt bus line and the drain-shunt bus line, and in the subsequent manufacturing processing to trimming and removal, even if unexpected electrical shock is applied, potential difference cannot be developed between the scanning and signal lines so as to prevent shorting between the scanning lines and signal lines due to insulation breakdown.
The method of manufacturing an active matrix substrate plate according to the 79th aspect of this invention relates to the 19th aspect of this invention, wherein, on the outside of a display surface where the pixel regions are arranged in a matrix, a gate-shunt bus line is formed for connecting the respective scanning line, and on the outside of the display surface, a drain-shunt bus line is formed for connecting the respective signal line, and the gate-shunt bus line and the drain-shunt bus line are connected at least at one point, and when manufacturing the active matrix substrate plate, in the first step, excepting the gate-shunt bus line for connecting respective scanning line, removing the first conductor layer by etching; in the third step, leaving so as to superimpose the drain-shunt bus line for connecting respective signal line on the gate-shunt bus line at one point at least and removing the second conductor layer by etching; and in the fourth step, removing by etching the protective insulation layer above a superposition location of the gate-shunt bus line and the drain-shunt bus line, and irradiating the superposition location with a laser beam to fuse and short circuit the gate-shunt bus line and the drain-shunt bus line by punching through the gate insulation layer.
This method provides the same beneficial effects as described above.
The method of manufacturing an active matrix substrate plate according to the 80th aspect of this invention relates to one according to one of the 20th to the 25th aspects of this invention, wherein, on the outside of a display surface where the pixel regions are arranged in a matrix, a gate-shunt bus line is formed for connecting the respective scanning line, and on the outside of the display surface, a drain-shunt bus line is formed for connecting the respective signal line, and the gate-shunt bus line and the drain-shunt bus line are connected at least at one point, and when manufacturing the active matrix substrate plate, in the first step, excepting the gate-shunt bus line for connecting respective scanning line, removing the conductor layer by etching; in the second step, removing by etching the metallic layer and the semiconductor layer above the gate-shunt bus line; in the third step, leaving so as to superimpose the drain-shunt bus line for connecting respective signal line on the gate-shunt bus line at one point at least and removing the transparent conductive layer, and next, removing the metallic layer and the n+ amorphous silicon layer where exposed by etching; and in the fourth step, removing by etching the protective insulation layer on top of a superposition location of the gate-shunt bus line and the drain-shunt bus line, and irradiating the superposition location with a laser beam to fuse and short circuit the gate-shunt bus line and the drain-shunt bus line by punching through the gate insulation layer.
This method provides the same beneficial effects as described above.
The method of manufacturing an active matrix substrate plate according to the 81st aspect of this invention relates to the 18th aspect of this invention, wherein, on the outside of a display surface where the pixel regions are arranged in a matrix, a high resistance line for connecting adjacent signal lines or for connecting a signal line and a common wiring line is provided, and when manufacturing the active matrix substrate plate, in the second step, excepting the portion to form the high resistance line, removing the semiconductor layer by etching; and in the third step, removing by etching the metallic layer and the transparent conductive layer above the portion to form the high resistance line and then removing the n+ amorphous silicon layer where exposed by etching.
This method enables to negate any potential developed by unexpected electrical shock applied the signal line by dispersing the potential to adjacent signal lines or to common wiring lines so that it is possible to prevent shorting due to insulation breakdown between the signal lines and the scanning lines or changes in the properties of the TFT in the pixel region.
The method of manufacturing an active matrix substrate plate according to the 82nd aspect of this invention relates to the 19th aspect of this invention, wherein, on the outside of a display surface where the pixel regions are arranged in a matrix, a high resistance line for connecting adjacent signal lines or for connecting a signal line and a signal line linking line connected to a common wiring line is provided, and when manufacturing the active matrix substrate plate, in the second step, excepting the portion to form the high resistance line, removing the semiconductor layer by etching; in the third step, excepting the signal line linking line, removing by etching the second conductor layer above the portion to form the high resistance line, and then removing by etching the n+ amorphous silicon layer where exposed; and in the fourth step, removing by etching a portion of the protective insulation layer above the signal line linking line, and a portion of the protective insulation layer and the gate insulation layer above the common wiring line, and in the subsequent steps, through the opening section formed in the protective insulation layer above the signal line linking line and the opening section formed in the protective insulation layer and the gate insulation layer above the common wiring line, the signal line linking line and the common wiring line are connected by silver beading.
This method provides the same beneficial effects as described above.
The method of manufacturing an active matrix substrate plate according to the 83rd aspect of this invention relates to the 20th or the 21st aspect of this invention, wherein, on the outside of a display surface where the pixel regions are arranged in a matrix, a high resistance line for connecting adjacent signal lines or for connecting a signal line and a common wiring line is provided, and when manufacturing the active matrix substrate plate, in the second step, excepting the portion to form the high resistance line, removing the metallic layer and the semiconductor layer by etching; and in the third step, removing by etching the transparent conductive layer above the portion to form the high resistance line and then removing the metallic layer and the n+ amorphous silicon layer where exposed by etching, thereby forming the signal line and the high resistance line using a same step.
This method provides the same beneficial effects as described above.
The method of manufacturing an active matrix substrate plate according to the 84th aspect of this invention relates to one according to one of the 22nd to the 25th aspects of this invention, wherein, on the outside of a display surface where the pixel regions are arranged in a matrix, a high resistance line for connecting adjacent signal lines or for connecting a signal line and a signal line linking line connected to a common wiring line is provided, and when manufacturing the active matrix substrate plate, in the second step, excepting the portions to form the signal line linking line and the high resistance line, removing the metallic layer and the semiconductor layer by etching; in the third step, removing by etching the transparent conductive layer above the portion to form the high resistance line and then removing the metallic layer and the n+ amorphous silicon layer where exposed by etching, thereby making the signal line and the high resistance line in a same step; in the fourth step, removing by etching a portion of the protective insulation layer above the signal line linking line, and a portion of the protective insulation layer and the gate insulation layer above the common wiring line, and in the subsequent steps, through the opening section formed in the protective insulation layer above the signal line linking line and the opening section formed in the protective insulation layer and the gate insulation layer above the common wiring line, the signal line linking line and the common wiring line are connected by silver beading.
This method provides the same beneficial effects as described above.
The method of manufacturing an active matrix substrate plate according to the 85th aspect of this invention relates to the 18th aspect of this invention, wherein, on the outside of a display surface where the pixel regions are arranged in a matrix, where adjacent signal lines are connected to each other across the island-shaped semiconductor layer comprised by amorphous silicon above the floating electrode formed concurrently with the scanning lines, or the signal line is connected to the common wiring line across the island-shaped semiconductor layer comprised by amorphous silicon above the floating electrode formed concurrently with the scanning lines, and when manufacturing the active matrix substrate plate, in the first step, excepting the floating electrode, removing the conductor layer by etching; in the second step, leaving an island-shaped semiconductor layer in a portion above the floating electrode, and removing the semiconductor layer; and in the third step, removing by etching the metallic layer and the transparent conductive layer so as to connect the adjacent signal lines or the signal line to the common wiring line across the island-shaped semiconductor layer, and then removing the n+ amorphous silicon layer where exposed by etching.
This method provides the same beneficial effects as described above.
The method of manufacturing an active matrix substrate plate according to the 86th aspect of this invention relates to the 19th aspect of this invention, wherein, on the outside of a display surface where the pixel regions are arranged in a matrix where adjacent signal lines are linked to each other across the island-shaped semiconductor layer comprised by amorphous silicon above the floating electrode formed concurrently with the scanning lines, or the signal line is connected to the signal line linking line connected to the common wiring linking line across the island-shaped semiconductor layer comprised by amorphous silicon above the floating electrode formed concurrently with the scanning lines, and when manufacturing the active matrix substrate plate, in the first step, excepting the floating electrode, removing the conductor layer by etching; in the second step, leaving an island-shaped semiconductor layer in a portion above the floating electrode, and removing the semiconductor layer; in the third step, removing by etching the metallic layer and the transparent conductive layer so as to connect the adjacent signal lines or the signal line to the signal line linking line across the island-shaped semiconductor layer, and then, removing the n+ amorphous silicon layer where exposed by etching; and in the fourth step, removing by etching a portion of the protective insulation layer above the signal line linking line, and a portion of the protective insulation layer and the gate insulation layer above the common wiring line, and in the subsequent steps, through the opening section formed in the protective insulation layer above the signal line linking line and the opening section formed in the protective insulation layer and the gate insulation layer above the common wiring line, the signal line linking line and the common wiring line are connected by silver beading.
This method provides the same beneficial effects as described above.
The method of manufacturing an active matrix substrate plate according to the 87th aspect of this invention relates to the 20th or the 21st aspect of this invention, wherein, on the outside of a display surface where the pixel regions are arranged in a matrix where adjacent signal lines are linked to each other across the semiconductor layer comprised by amorphous silicon above the floating electrode formed concurrently with the scanning lines, or the signal line is connected to the common wiring line across the semiconductor layer comprised by amorphous silicon above the floating electrode formed concurrently with the scanning lines, and when manufacturing the active matrix substrate plate, in the first step, excepting the floating electrode, removing the conductor layer by etching; in the second step, leaving so as to link the adjacent signal lines or the signal line and the common wiring line, removing the metallic layer and the semiconductor layer by etching; and in the third step, removing by etching the transparent conductive layer on top of a portion where the adjacent signal lines or the signal line and the common wiring line are connected, and then removing the metallic layer and the n+ amorphous silicon layer where exposed by etching, thereby making the signal line and the common wiring line and the semiconductor layer of the linking portion in a same step.
This method provides the same beneficial effects as described above.
The method of manufacturing an active matrix substrate plate according to the 88th aspect of this invention relates to one of the 22nd to the 25th aspects of this invention, wherein, on the outside of a display surface where the pixel regions are arranged in a matrix, where adjacent signal lines are connected to each other across the semiconductor layer comprised by amorphous silicon above the floating electrode formed concurrently with the scanning lines, or the signal line is connected to the signal line linking line connected to a common line linking line across the semiconductor layer comprised by amorphous silicon above the floating electrode formed concurrently with the scanning lines, and when manufacturing the active matrix substrate plate, in the first step, excepting the floating electrode, removing the conductor layer by etching; in the second step, removing the metallic layer and the semiconductor layer by etching so as to connect the adjacent signal lines or the signal line and the common wiring line linking line; in the third step, removing by etching the transparent conductive layer above the adjacent signal lines or a portion where the signal line and the common wiring line linking line are linked, and then removing the metallic layer and the n+ amorphous silicon layer where exposed by etching, thereby making the signal line and the common wiring line linking line and the semiconductor layer at the linked portion in a same step; in the fourth step, removing by etching a portion of the protective insulation layer above the signal line linking line, and a portion of the protective insulation layer and the gate insulation layer above the common wiring line, and in the subsequent steps, through the opening section formed in the protective insulation layer above the signal line linking line and the opening section formed in protective insulation layer and the gate insulation layer above the common wiring line, the signal line linking line and the common wiring line are connected by silver beading.
This method provides the same beneficial effects as described above.
The method of manufacturing an active matrix substrate plate according to the 89th aspect of this invention relates to one according to one of the 58th to the 73rd aspects of this invention, wherein, in the fourth step, leaving the protective insulation layer so that the perimeter section of the protective insulation layer descends vertically to cover a portion of the lateral surface of the channel gap lateral section where amorphous silicon layer is exposed, and the outer protective insulation layer and the semiconductor layer are removed by etching.
This method for manufacturing an active matrix substrate plate, because a portion of both lateral surfaces of the semiconductor layer extending in the direction of the channel section in the TFT section is covered by the protective insulation layer, charge leaking through the lateral surface of the semiconductor layer can be prevented to secure reliability of the TFT section.
The method of manufacturing an active matrix substrate plate according to the 90th aspect of this invention relates to the 89th aspect of this invention, wherein, in the second step, removing by etching the semiconductor layer and the gate insulation layer on the outside of at least one end section of the channel gap to form an opening section to reach the gate electrode or the scanning line; and in the fourth step, the opening section and a perimeter section that formed in the protective insulation layer are intersected, and leaving the protective insulation layer above the thin film transistor so that the perimeter section of the protective insulation layer descends vertically to cover a portion of the lateral surface of the channel gap lateral section where amorphous silicon layer is exposed through the opening section, and removing the outer protective insulation layer and the semiconductor layer by etching.
This method provides the same beneficial effects as described above.
The method of manufacturing an active matrix substrate plate according to the 91st aspect of this invention relates to the 90th aspect of this invention, wherein, in the second step, the opening section is formed on both outer lateral sections of the channel gap.
This method provides the same beneficial effects as described above.
The method of manufacturing an active matrix substrate plate according to the 92nd aspect of this invention relates to one according to one of the 58th to the 61st, and the 66th to the 73rd aspects of this invention, wherein, in the second step, removing by etching the semiconductor layer and the gate insulation layer on the outer end section of the channel gap at least on the scanning line side to form an opening section so that at least one portion is included in the scanning line; and in the fourth step, the opening section and a perimeter section formed in the protective insulation layer are intersected, and leaving the protective insulation layer above the thin film transistor so that the perimeter section of the protective insulation layer descends vertically to cover a portion of the lateral surface of the channel gap lateral section where amorphous silicon layer is exposed through the opening section, and removing the outer protective insulation layer and the semiconductor layer by etching.
In these methods for manufacturing an active matrix substrate plate, when etching the metallic layer of the signal line or the transparent conductive layer, even if the etching solution infiltrated through the opening section punched through the gate insulation layer above the gate electrode and the semiconductor layer and a portion of the semiconductor layer is corroded, because the opening section on the scanning line side is formed so as to be contained in the scanning line, there is no danger of the conductor layer at the base section of the gate electrode to be corroded seriously, so that the signal from the scanning line driver can be sent normally to the gate electrode of the TFT section.
The methods of manufacturing an active matrix substrate plates according to the 93rd and the 94th aspects of this invention relate to the 89th and the 92nd aspects of this invention, respectively, wherein, in the first step, on top of the transparent insulation substrate plate, not less than one layer of a conductor layer and an upper layer of a conductive etching protection layer are laminated to make the conductor layer.
In these methods of manufacturing an active matrix substrate plate, during etching of the metallic layer of the signal line or the transparent conductive layer, it is possible to prevent corrosion of the gate electrode or conductive layer below the scanning line due to infiltration of etching solution through the opening section punched through the gate insulation layer above the gate electrode and the semiconductor layer, thereby preventing severing of the base section of the gate electrode or the scanning line.
The methods of manufacturing an active matrix substrate plates according to the 95th and the 96th aspects of this invention relate to according to the 93rd and the 94th aspects of this invention, respectively, wherein at least one layer of the conductive layer is formed by Al or an alloy of primarily Al, and the conductive etching protection layer is formed by Ti, Ta, Nb or an alloy containing primarily one metal of preceding metals, or by Ti, Ta, Nb, Cr or a nitride film of an alloy containing primarily one metal of preceding metals.
This method provides the same beneficial effects as described above.
The method of manufacturing an active matrix substrate plate according to the 97th aspect of this invention relates to one according to the 59th, the 61st, the 67th, the 69th, the 71st, and the 73rd aspects of this invention, wherein, in the fourth step, the protective insulation layer is left unetched so as to cover a connection section between the conductor layer and the transparent conductive layer.
In the method for manufacturing an active matrix substrate plate according to the 59th or the 61st aspect of this invention, when the first conductor layer and the metallic layer of the second conductor layer are comprised by a same type of metals or they are to be etched by a same etching solution, at the contact section of the first conductor layer and the transparent conductive layer, when removing by etching the metallic layer above the transparent conductive layer after the opening section is formed on the protective insulation layer, it is possible to prevent the etching solution to infiltrate through the transparent conductive layer to corrode the first conductor layer.
Also, the method for manufacturing an active matrix substrate plate according to one of the 67th, the 69th, the 71st, or the 73rd aspects of this invention, when at least one layer of the first conductor layer is comprised by Al or an alloy of primarily Al, and if a hydrofluoric type acid is used to etch the opening section in the protective insulation layer, at the contact section of the first conductor layer and the transparent conductive layer, during etching forming of the opening section on the protective insulation layer, it is possible to prevent the etching solution to infiltrate through the transparent conductive layer to corrode Al or an alloy of primarily Al in the first conductor layer.
The method of manufacturing an active matrix substrate plate according to the 98th aspect of this invention relates to one according to one of the 18th, the 20th, the 21st, the 58th to the 61st, and the 66th to the 73rd aspects of this invention, wherein, in the first step, the conductor layer is removed by etching so as to leave the light blocking layer to superimpose at least on one section of the perimeter section of each pixel region.
In the method for manufacturing these active matrix substrate plates, because the light blocking layer is provided on the active matrix substrate plate side, it is possible to reduce the black matrix of the color filter substrate plate that needs to have a large superpositioning margin, thereby enabling to improve the aperture factor.
The method of manufacturing an active matrix substrate plate according to the 99 aspect of this invention relates to one according to one of the 18th, the 19th, the 58th to the 65th aspects of this invention, wherein, in the second step, the semiconductor layer is removed by etching so as to leave a portion where the scanning line and the signal line are intersected.
In this method for manufacturing an active matrix substrate plate, because the semiconductor layer is laminated on the gate insulation layer at the intersection point of the scanning line and the signal line, dielectric strength between the scanning line and the signal line is improved.